Smith-Waterman算法在脉动阵列上的实现及分析

Smith Waterman算法是一种经典的序列比对算法 ,在双序列比对的情况下具有比较好的性能 ,但是在大规模的序列比对时 ,其性能并不能令人满意 .脉动式阵列和Smith Waterman算法有比较好的吻合性 .该文通过在龙芯 1号处理器上附加一个脉动式阵列的协处理器 ,构建了硬件模型 .通过模拟器的验证 ,附加了协处理器的龙芯 1号的性能与没有附加协处理器时的性能之比接近于线性 .该文最后根据硬件模型和模拟器的性能数据 ,具体分析了系统各个方面对性能提高的影响     

一维和二维快速正弦变换

正弦变换在时间序列分析中经常用到,所以考虑正弦变换算法是必要的。这里给出用FPT程序计算N-1点实序列正弦变换的快速算法。该算法可以减少存贮和计算量,对N-1点实序列的正弦变换约需Nlog_2(2~(1/2)N~2)次实数乘、加运算,而直接计算要用(N-1)~2次。该法也被推广到二维离散工弦变换,对(M-1)×(N-1)点的二维实序列正弦变换约需MNlog_2(2M~2N~2)次实数乘、加运算,而直接算法要用(M-1)(N-1)(M+N-2)次。     

基于混沌和Walsh变换的二值图像加密算法

提出一种基于混沌映射和Walsh变换的二值图像加密算法。首先对二值图像进行混沌加密,再对混沌加密后的图像用Walsh变换进行置乱,实现图像信息的高强度加密。运用Walsh变换可以在很大程度上节约计算时间。仿真实验结果表明,混沌序列与Walsh变换相结合的方法加密强度高,计算时间短。     

合成序列变换的加速收敛

设{S_n}是待加速的序列,limS_n=S。按[1]考虑序列变换t_k:{S_n}→{t_k~(n),k=1,2。记 N_k={{S_n}:?N,n>N,t_k~(n)=S},称N_k(k=1,2)是变换t_k的核。定义变换T T:{S_n}→{T_n}, ?_n,T_n=(1-α_n)t_1~(n)+α_nt_2~(n),并规定,若S_n∈N_1,则?n,α_n=0,若S_n∈N_2,则?n,α_n=1。此时称T是秩为2的合成序列变换。 记N是变换T的核,则N?N_1∪N_2。由此说明变换T优于变换t_1和变换t_2。     

鲁棒控制基准设计问题:倒立摆控制

1　系统概述本系统由水平移动的小台车及由其支撑的单节倒立摆构成 .控制输入量是拖动小台车的直流伺服电机的电枢电压 ,被控制量是摆的偏角和小台车的位移 .系统的构成示意如图 1.图 1　系统示意图2　系统的运动方程2 .1驱动电机记电枢电压和电流分别为v(t) (V)和ia(t) (A) ,则电机的动态方程为Raia(t) +Ladiadt(t) +KEω(t) =v(t) ,(1)τ(t) =KTia(t) . (2 )其中Ra(Ω)和La(H)分别为电枢电阻和电枢电感 ,KE(Vs/rad)为反向电势系数 ,KT(Nm/A)为力矩系数 ,一般可取KE =KT.ω(t) (rad/s)表示电机的转子的角速度 ,τ(t) (Nm)为电机…     

基于VLIW的并行可配置ECC协处理器结构研究与设计

采用专用指令密码处理器的设计方法,提出了一种基于超长指令字(VLIW)的并行可配置椭圆曲线密码(ECC)协处理器结构.该协处理器结构对点加、倍点并行调度算法进行了映射,功能单元微结构采用了可重构的设计思想.整个ECC协处理器具有高度灵活性与较高运算速度的特点.能支持域宽可伸缩的GF(P)与GF(2m)有限域上的可变参数Weierstrass曲线.实验结果表明,GF(p)域上192 bit的ECC点乘运算只需要0.32ms,比其它同类芯片运算速度提高了1.1～3.5倍.     

二阶加滞后连续模型的直接辨识

1　引言本文提出了一种新的基于阶跃响应数据直接辨识二阶连续模型参数的算法 ,对文献 [1 ]中的算法进行了推广 ,适用于解决实际工业系统辨识问题 .2　直接法阶跃响应辩识考虑有滞后环节的过阻尼二阶对象G(s) =K(T1 s+ 1 ) (T2 s+ 1 ) e-θs. (1 )阶跃输入幅度为 α时 ,阶跃响应为y(t) =αK 1 -T1 T1 -T2 e- t-θT1+ T2T1 -T2 e- t-θT2 ,t≥θ. (2 )令 T1 =βT2 ,加入白噪声 ω(t) ,则y(t) =αK 1 -ββ -1 e- t-θβT2 + 1β -1 e- t-θT2 +ω(t) ,t≥θ. (3)由于 0≤t<θ时 ,y(t) =ω(t) ,从而∫τ0 y(t) dt=∫τθy(t) dt+ ∫θ…     

找到不可约多项式的研究与FoxPro程序实现

在扩频通信与传统的密码体制中广泛使用的伪随机序列,大部分是利用不可约多项式通过反馈位移寄存器和其他非线性逻辑来产生的。同时,多项式理论,特别是不可约多项式的性质对分析各种伪随机序列有着特殊的作用。 (1)找到非负整系数不可约多项式的原理 建立非负整系数多项式与正整数的符号对应和运算对应:设α_0,α_1,α_2,α_3,…,α_n是非负整数,2,3,5,7,…,p_n是n+1个相邻的素数。用正整数2~(α_0)3~(α_1)5~(α_2)(?)p_n~(α_n)表示非负整系数多项式α_0+α_1x+α_2x~2+…+α_nx~n。记作:{α_0+α_1x+α_2x~2+…+α_nx~n}←→2~(α_0)3~(α_1)5~(α_2)(?)p_n~(α_n)。     

ICL7129型单片4(1/2)位A/D转换器原理与应用

ICL7129是美国英特西尔(Intersil)公司于八十年代后期研制的高性价比4(1/2)位液晶显示单片A/D 转换器。这种芯片目前已进入国内市场,由它构成的DT/930F、DT/930F+型4(1/2)位数字万用表也已面市。本文重点介绍其工作原理和典型应用。     

二维离散哈特莱变换的乘法复杂性

本文研究了长度为2~n×2~n(n为正整数)二维离散哈特莱(Hartley)变换的乘法复杂性。虽然DHT(2~n;2)的变换核cas[2π(kp+lq)/2~n]不象DFT(2~n,2)的变换核exp[—2πj(kp+lq)/2~n]那样可以分离成一维DHT变换核的乘积,但是DHT(2~n;2)可以利用线性同余组和环结构转换成1个DHT(2~(n-1);2)和(3/2)2~n个一维奇DHT.一维奇DHT可以简化为一维DHT的核CHT的直和,在有理数域Q上计算长度为2~n的二维离散DHT(2~n;2)所需的最少实乘次数为2~(2n+1)—6(n—1)2~n—8。所以二维DHT(2~n;2)和相应的实DFT(2~n;2)具有相同的乘法复杂性。     

LS SIMD协处理器控制器设计

LS SIMD协处理器是用于底层图像理解的16位定点嵌入式阵列处理器,该处理器除SIMD固有的数据并行性外,还具有三级流水和三组指令并发执行的并行性。主要阐述LS SIMD协处理器的三级流水线和三组指令并发执行的基本可重用的主控制器设计。     

Hardware to support runtime intelligence

An associative memory system that is specialized to support the syntax and associated pattern-matching rules common to declarative expression is discussed. A coprocessor board based on an array of custom VLSI chips that combine both logic and memory is described. It is shown how this hardware supports a number of popular intelligent-system architectures. Application to querying a dynamic database is considered     

Pattern-addressable memory

The pattern associative memory (PAM), a custom associative memory chip specialized to handle the syntax and associated pattern-matching rules common to a range of symbolic processing applications, is discussed. The applications of particular interest are those in which runtime information is captured in the form of a database of declarative expressions. The structure and functioning of an array of these chips, which forms an associative coprocessor for a workstation are described. PAM implementation is addressed     

一种改进的嵌入式SIMD协处理器设计

论文介绍的SIMD协处理器是用于低层图像理解的16位定点嵌入式阵列处理器。该协处理器采用load/store体系结构,并且除SIMD固有的数据并行性外,还具有三级流水和三组指令并发执行的并行性。三组指令并发执行使数据交换操作和其它类型操作并发执行,从而实现了数据交换操作的隐含执行,大大减少了通信和I/O操作的开销。     

矩阵乘协处理器上BLAS level-3运算的设计

BLAS level 3运算的计算复杂度较高,其往往成为应用的性能瓶颈。采用线性阵列结构的矩阵乘协处理器可实现高性能、高效的矩阵乘运算。在矩阵乘协处理器上高效实现BLAS level 3运算,对大规模科学与工程仿真应用的计算加速至关重要。以矩阵乘为核心运算,结合线性阵列的结构特点,提出了矩阵乘协处理器上BLAS level 3运算的设计,并构建了相应的性能分析模型。实验结果表明,矩阵乘协处理器上SYMM、SYRK和TRMM运算的计算效率分别达到了99%,98%和80%,与SW26010和NVIDIA V100 GPU上矩阵运算的计算效率相比,最高提升了31%。     

A detailed statistical study on selection of optimum IRS LISS pixel configuration for development of water quality models

Whenever remote sensing data are used in conjunction with in situ measurements for modelling a physical phenomenon, the major problem is in the selection of digital data which are representative of the ground points under consideration. This problem can be solved in most cases, including the present study on water quality modelling, by placing dependence not on a single pixel number of the estimated point in question. The study reports the analyses of different size pixel arrays for date of 11 April 1993 in the form of CCT obtained from NRSA, Hyderabad. In order to select the best pixel array configuration to represent the sample station point on the multi-band image, nested arrays of pixels for 4 bands with 7 different sizes are sampled at 52 different sampling stations in the Gautami-Godavari river estuary where water quality variables had been measured. These seven array sizes, namely three symmetric arrays of sizes: 5 by 5, 3 by 3 and 1 by 1 and 4 non-symmetrical arrays of 2 by 2 with the centre pixel located at different corners of each 2 by 2 arrays are analysed using Analysis of Variance \[ANOVA] and t -test. The data bank of 52 by 7 by 4 average pixel values was available for ANOVA and t -test. The results of ANOVA highlight the importance of considering all four IRS bands and each band contains different information regarding physical conditions of the study points, sensor characteristics and water and atmospheric responses. The pixel data are also significantly different at 99 per cent confidence level among sample locations. This indicated that all the four bands have to be considered in developing water quality models. The results of t -test proved that the 5 by 5 and 3 by 3 array sizes are the best among the 7 configurations, but no significant difference is indicated between the two array types. The 3 by 3 window is selected for water quality modelling because it is smaller and involves less computational work.     

A high speed multi-level-parallel array processor for vision chips

This paper proposes a high speed multi-level-parallel array processor for programmable vision chips.This processor includes 2-D pixel-parallel processing element(PE)array and 1-D row-parallel row processor(RP)array.The two arrays both operate in a single-instruction multiple-data(SIMD)fashion and share a common instruction decoder.The sizes of the arrays are scalable according to dedicated applications.In PE array,each PE can communicate not only with its nearest neighbor PEs,but also with the next near neighbor PEs in diagonal directions.This connection can help to speed up local operations in low-level image processing.On the other hand,global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP array.The array processor was implemented on an FPGA device,and was successfully tested for various algorithms,including real-time face detection based on PPED algorithm.The results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.     

Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design

In this paper, we have proposed an efficient method for integrating longer pipeline coprocessors with SPARCv8 compliant processor implementations that requires minimum changes in the existing processor pipeline. The proposed integration method is independent of the length of the coprocessor pipeline. We have used COordinate Rotation DIgital Computer (CORDIC) core as the coprocessor that has been integrated with SPARCv8 based LEON3 processor. Only a subset of the coprocessor instructions defined in the Instruction Set Architecture (ISA) are required in our proposed method. The required synchronisation of data and control signals between the coprocessor and LEON3 pipeline has been presented in detail. The performance of the resulting closely-coupled design is compared with bus-based integration in terms of speed, power and area in the System-on-Chip (SoC) design, and both FPGA and ASIC results are reported. Our proposed integration method shows significant improvements over bus-based method for applications that require consecutive coprocessor operations in terms of CPI metric along with substantial reduction in number of cycles. Similar strategy can be employed for integration with coprocessors having different pipeline lengths.     

基于特征点匹配和哈希法的图像检索方法

提出一种基于点特征匹配和几何型哈希法的图像检索方法。利用小波变换提取图像的突变点，以点为辜心划定一小块区域，将图像划分成图像块。提取块的低层次特征矢量，将两幅图像之间的匹配转换成图像块之间的匹配。并采用几何型哈希索引方法实现图像的快速检索。实验证明，这种方法能够取得较高的检索精度，且对图像形变以及局部遮挡等都有较好的适应能力。     

A heuristic search-based motion correspondence algorithm using fuzzy clustering

Motion correspondence problem between many feature points of consecutive frames is computationally explosive. We present a heuristic algorithm for finding out the most probable motion correspondence of points in consecutive frames, based on fuzzy confidence degrees. The proposed algorithm consists of three stages: (i) reduction of the search space for candidate points of association, (ii) pairwise association cost estimation and (iii) complete association of every feature point between the consecutive frames. In the first stage, all the points in a frame, frame t-1 are grouped into several groups by using fuzzy clustering. This is done with a Euclidean distance as a similarity measure between the points. The points in the following frame, frame t are also clustered into the same number of groups with respect to the cluster centers of the previous frame. The association between the points of the consecutive frames is allowed only for the points that belong to the same group in each frame. In the second stage, the cost of each association of a point in frame t-1 with a point in frame t is estimated by using motion constraints that are based on the velocity vector and the orientation angle of each point. The cost is measured as a fuzzy confidence degree of each head point, i.e., a point in frame t-1, belonging to each measurement, i.e., a point in frame t. In the final stage, we search for the most likely associations among all the possible mappings between the feature points in the consecutive frames. A search tree is constructed in such a way that an ith level node represents an association of ith node in frame t-1 with a node in frame t. We devise a heuristic function of an admissible A* algorithm by using the pairwise association cost developed in the second stage. Experimental results show an accuracy of more than 98%.