新型属性图文法反应式规约验证方法

属性图文法广泛应用在软件设计阶段建模和分析阶段。命题式时序逻辑（propositional temporal logic）无法直接表达建模实体包含随时间演化的关联属性反应式规约,提出一种可支持通用图文法转换系统中相应规约的验证方法,通过引入标记节点及属性,将包含相应关联属性的规约公式等价转换为命题式时序逻辑,从而可以间接支持该类型规约的验证。以流行的对象式属性图文法模型检测工具GROOVE为平台,结合启发案例,验证了所提出方法的有效性。     

基于图文法的动态软件体系结构支撑环境

使用类型化的属性图及其图文法来直观而形式地刻画软件体系结构和体系结构风格,用图转换来刻画动态体系结构的重配置行为.基于这种刻画,构建了一个动态软件体系结构支撑环境.该环境一方面,通过一个基于图文法的编辑器来支持体系结构图模型的可视化构造和操纵;另一方面,基于内置运行时体系结构技术实现了体系结构图模型在具体系统中的物理实施,并使得图模型上的图转换操作可以自动映射到实际系统的动态重配置上.再加上一系列的辅助设施,形成了一个较为完整的基于图文法的动态软件体系结构支撑环境.     

一种图文法制导的软件体系结构开发环境Artemis-GADE

图形化、集成化的软件体系结构开发环境对于推动软件体系结构相关技术的研究和应用具有重要的意义.提出了一种基于图文法的可视化编辑环境生成机制.对于给定的软件体系结构风格的图文法描述,可以自动生成相应的图文法制导的体系结构编辑工具.与常见的基于Meta-Model的开发环境相比,这种图文法制导的开发方式更多地利用了相应软件体系结构风格的内在语义,从而提高了环境的易用性和可靠性.设计并实现了一个原型系统Artemis-GADE(graph grammar-directed architecture development environment),初步验证了上述途径的可行性.     

图文法EGG在设计模式中的应用

对图变换和可视化语言的研究激发并促进了图文法的研究和发展。作为一维字符文法的扩展,图文法可以形式化描述二维空间中的对象,如图像、图形和表格等,为它们的定义、生成、变换及分析提供理论和技术上的支持。设计模式是可复用面向对象软件的基础,通常以二维图的形式来表示。为了与用户多样化的需求相适应,设计模式经常需要在不改变系统基本结构的情况下进行演化。本文讨论了图文法EGG及其形式化方法在设计模式的演化中的应用,聚焦在图变换和图解析两方面。前者用EGG格式的产生式作为图重写式来指导图的每一次变换,以确保相应设计模式演化每一步的正确性;后者用EGG文法机制来对图进行归约,以检查随意演化后的设计模式是否合法。     

自动生成前端编译程序的一种方法*

本文构造的XYZ/NGAE系统是建立在属性文法基础上的前端编译程序自动生成系统．本文在概述了属性文法及其描述语言之后，简要地介绍该系统的体结构以及为减少空间开销而采用的优化措施．     

基于属性文法和语义网络的综合知识表示模型

本文提出了一个属性文法计算模型与语义网络表示模型相结合的综合知识表示模型.根据形式化的语义网络表示模型和属性文法的特点,该模型使用属性文法的符号建立了一些适合于语义网络表示模型的语法和语义规则模式,并且可通过扩充的属性文法的解释器来实现推理.     

FORTRAN语言的一个属性文法

本文介绍了用属性定义语言ALADIN写的FORTRAN语言的属性文法。该文法描述了FORTRAN语言的语法结构及其静态语义,包括作用域规则、说明的建立、表达式分析和出错处理等。     

综合知识表示模型MAS的属性文法推理机制

根据文献［２］中提出了的基于属性文法和语义网络的综合知识表示模型ＭＡＳ，本文提出了关于实现该ＭＡＳ推理机制的基本算法，并且通过实例对该算法进行了说明，最后，证明了基于ＭＡＳ模板的属性文法是Ｌ－ＡＧ和ＩＭＡＳ的解是完全的结论。     

图文法综述

形式语言理论对计算机科学的发展起了重大的作用,作为对传统字符文法扩展的图文法的形式化研究,其重要意义是不言而喻的.本文在概述图文法的产生、发展和现状的基础上,着重介绍了从一维字符文法扩展到二维图文法所出现的新问题,以及在形式化处理上引出的新方法,其中最主要的是嵌入问题的解决、文法类型的划分和成员问题的判定.文中以目前较为流行的图文法为例,特别是一些典型的上下文无关和上下文相关的图文法,对上述的问题进行了深入的讨论,指出了现有方法中的一些不足之处,并展望了图文法今后值得研究的问题和方向.     

一种有效的结点标号上下文无关图文法分析算法

本文讨论了上下文无关图文法的性质，并证明了图文法推导具有独立性．本文还给出了一种有效的上下文无关图文法分析算法，它具有多项式时间复杂性，并给出了算法的正确性证明．该算法已经用Ｃ语言实现．     

Issues in distributed timed model checking

In this work we present Zeus, a distributed timed model checker that evolves from the TCTL model checker Kronos [13] and that currently can handle backwards computation of reachability properties [2] over timed automata [3].Zeus was developed following a software architecture-centric approach. Its conceptual architecture was conceived to be sufficiently modular to house several features such as a priori graph partitioning, synchronous and asynchronous computation, communication piggybacking, delayed messaging, and dead-time utilization.Surprisingly enough, early experiments pinpointed the difficulties of getting speedups using asynchronous versions and showed interesting results on the synchronous counterpart, although being intuitively less attractive.     

基于XYZ/ADL的异步Web服务组合描述与验证

Web服务组合为研究对象,重点讨论了服务组合中异步通信行为和时间属性的形式化描述和验证.首先,从软件体系结构角度分析Web服务组合,采用基于时序逻辑的XYZ/ADL描述Web服务的交互行为和时间属性;然后,提出一种符合模型检测工具UPPAAL规约的时间异步通信模型TACM;最后,实现了XYZ/RE通信命令到TACM的映...     

从用户需求到软件规约：一种问题变换的方法

研究的目的是在获取用户需求和领域描述的基础上规约出对软件规格的描述.提供了一种实现从用户需求到软件规约的平滑和可推理的变换方法.在深入研究问题框架方法的基础上,采用Hoare 的通信顺序进程语言CSP及Lai的最弱环境演算符实现了整个问题图的变换,且导出的软件规格是具有高抽象粒度的程序代码模型,能够被FDR模型检测工具所验证.该工作为实现嵌入式软件开发从需求到软件代码、文档的自动转化及验证等奠定了理论基础.此外,把该理论与模型检测工具FDR联合起来会有助于提高嵌入式软件开发的效率和准确性.     

Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems

Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for mobile and ubiquitous systems. In this work, we present the internal architecture and design flow of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF), which integrates three techniques namely software component-based reuse, formal synthesis, and formal verification. Component reuse is based on a formal unified modeling language (UML) real-time embedded object model. Formal synthesis employs quasi-static and quasi-dynamic scheduling with multi-layer portable efficient code generation, which can output either real-time operating systems (RTOS)-specific application code or automatically generated real-time executive with application code. Formal verification integrates a model checker kernel from state graph manipulators (SGM), by adapting it for embedded software. The proposed architecture for VERTAF is component-based which allows plug-and-play for the scheduler and the verifier. The architecture is also easily extensible because reusable hardware and software design components can be added. Application examples developed using VERTAF demonstrate significantly reduced relative design effort as compared to design without VERTAF, which also shows how high-level reuse of software components combined with automatic synthesis and verification increases design productivity.     

Proof-carrying code from certified abstract interpretation and fixpoint compression

Proof-carrying code (PCC) is a technique for downloading mobile code on a host machine while ensuring that the code adheres to the host's safety policy. We show how certified abstract interpretation can be used to build a PCC architecture where the code producer can produce program certificates automatically. Code consumers use proof checkers derived from certified analysers to check certificates. Proof checkers carry their own correctness proofs and accepting a new proof checker amounts to type checking the checker in Coq. Certificates take the form of strategies for reconstructing a fixpoint and are kept small due to a technique for fixpoint compression. The PCC architecture has been implemented and evaluated experimentally on a byte code language for which we have designed an interval analysis that allows to generate certificates ascertaining that no array-out-of-bounds accesses will occur.     

VERTAF: an application framework for the design and verification of embedded real-time software

The growing complexity of embedded real-time software requirements calls for the design of reusable software components, the synthesis and generation of software code, and the automatic guarantee of nonfunctional properties such as performance, time constraints, reliability, and security. Available application frameworks targeted at the automatic design of embedded real-time software are poor in integrating functional and nonfunctional requirements. To bridge this gap, we reveal the design flow and the internal architecture of a newly proposed framework called verifiable embedded real-time application framework (VERTAF), which integrates software component-based reuse, formal synthesis, and formal verification. A formal UML-based embedded real-time object model is proposed for component reuse. Formal synthesis employs quasistatic and quasidynamic scheduling with automatic generation of multilayer portable efficient code. Formal verification integrates a model checker kernel from SGM, by adapting it for embedded software. The proposed architecture for VERTAF is component-based and allows plug-and-play for the scheduler and the verifier. Using VERTAF to develop application examples significantly reduced design effort and illustrated how high-level reuse of software components combined with automatic synthesis and verification can increase design productivity.     

A Safety Mechanism Using Software Patterns

Software patterns have been widely studied in order to reuse of design knowledge in software design phase. However, few patterns have been known in the area of safety. This paper addresses a mechanism for safety and its software pattern in a reactive system. We construct a pattern composed of a mechanism called an event checker including several software patterns to check scenarios, i.e., the order of events and their timing constraints. Next, we show examples of its implementation to railroad models using Java. Moreover, we discuss the safety in the domain of a reactive system by means of this event checker and its software reliability by using this pattern.     

2011 CAV award announcement

The 2011 CAV (Computer-Aided Verification) Award was presented on July 17, 2011 at the 23rd annual CAV conference in Snowbird, Utah to Thomas Ball and Sriram Rajamani of Microsoft Research for their contributions to software model checking, specifically the development of the SLAM/SDV software model checker, which successfully demonstrated computer-aided verification techniques on real programs.