Functional test environment for time-triggered control systems in complex MPSoCs

Many safety-critical and especially mixed-criticality computer systems are realized as a time-triggered (TT) system. Such systems execute one or more tasks according to a pre-determined scheduling. For the integration of functionality on such a TT MPSoC, not only the timing, but also the interplay of functional behavior and timing, needs to be validated.In this work we are proposing a new test environment for TT systems. Our proposed framework captures the TT system configuration, performs consistency checks and generates a fast executable simulation model. In the past, functional integration testing has been performed on a prototyping board, sometimes in a Hardware-in-the-Loop (HIL) configuration to support testing against a complex environment model. Compared to a simulation model, a HIL setup requires high effort, has a comparable low observability and is more difficult to debug. For this reason we propose the GALI (Globally Accurate, Locally Inaccurate) simulation model that combines an instruction accurate simulation engine with a global time-triggered scheduler. Thus, combining the low-level view on the implemented system with very good testability and debuggability.The proposed configuration and simulation platform accelerates the design and implementation of future TT systems. We evaluate our presented approach on a safety-relevant multirotor system.     

嵌入式系统虚拟原型平台的SystemC实现

提出一个基于SystemC的可配置嵌入式系统快速虚拟原型平台，它具有典型的片上系统结构，支持多层总线架构．作为SystemC事务处理级模型，该平台支持快速仿真和通信细化．将此平台应用于IEEE 802．11媒体访问控制器的设计，目前该系统正处于板级调试过程中．     

SystemC cosimulation and emulation of multiprocessor SoC designs

SystemC is an open source C/C++ simulation environment that provides several class packages for specifying hardware blocks and communication channels. The design environment specifies software algorithmically as a set of functions embedded in abstract modules that communicate with one another and with hardware components via abstract communication channels. It enables transparent integration of instruction-set simulators and prototyping boards. The authors describe a simulation environment that targets heterogeneous multiprocessor systems. They are currently working to extend their methodology to more complex on-chip architectures.     

Time-triggered architecture: a consistent computing platform

The time-triggered architecture provides a consistent computing platform for large complex applications and safety-relevant systems. TTA is already in use in railway systems, and the aerospace and automotive industries are beginning to adopt it, with first products making their way into the field     

Time-triggered buffers for event-based middleware systems

Application developers utilizing event-based middleware have sought to leverage domain-specific modeling for the advantages of intuitive specification, code synthesis, and support for design evolution. For legacy and cyber-physical systems, the use of event-based middleware may mean that changes in computational platform can result anomalous system behavior, due to the presence of implicit temporal dependencies. These anomalies are a function not of the component implementation, but of the model of computation employed for supporting system composition. In order to address these behavioral anomalies, the paper presents an approach where time-based blocks are inserted into the system to account for the temporal dependencies. An advantage of capturing the system composition in a domain-specific modeling language is the ability to efficiently refactor an application to include time-triggered, event-based schedulers. This paper describes how an existing event-based component topology can be modified to permit a time-triggered model of computation, with no changes to the existing component software. Further, the time-triggered components can be deployed alongside standard publish/subscribe methodologies. This strategy is beneficial to the maintenance of existing legacy systems upon upgrade, since the current operational mode could be maintained with minimal changes to the legacy software even under changes to the target platform which alter execution speed. These time-triggered layers are discussed in three permutations: fully triggered, start triggered, and release triggered. A discussion is provided regarding the limitations of each approach, and a brief example is given. The example shows how to apply these triggering approaches without the modification of existing components, but instead through the insertion of triggered buffers between legacy components.     

A SystemC/Matlab co-simulation tool for networked control systems

Real-time systems connected through packet networks belong to the family of networked control systems, and they can be easily destabilized by communication delay and packet losses, when they are not properly compensated. The largest part of the solutions available in the literature are mainly based on control and system theory where the parameters of the network are assumed to be given. This classical approach could be improved by designing at the same time the network, e.g., by introducing quality-of-service guarantees as currently done in teleconference applications. Such control/network co-design needs a simulation framework where both aspects are properly and jointly addressed. The paper addresses this topic starting from the discussion of its critical issues, and then proposing an accurate co-simulation tool based on SystemC and Matlab/Simulink. SystemC will be used for the network simulation and protocol design whereas Matlab/Simulink for plant modeling and control design.     

TT-BIP: using correct-by-design BIP approach for modelling real-time system with time-triggered paradigm

In order to combine advantages of real-time operating systems implementing the time-triggered (TT) execution model and model-based design frameworks, we aim at proposing a correct-by-design methodology that derives correct TT implementations from high-level models. This methodology consists of two main steps: (1) transforming the high-level model into an intermediate model which respects the TT communication principles and where all communications between components are simple send/receive interactions, and (2) transforming the obtained intermediate model into the programming language of the target platform. In this paper, we focus on the presentation of the transformational methodology of the first step of this design flow. This methodology produces a correct-by-construction TT model by starting from a high-level model of the application software in behaviour, interaction, priority (BIP). BIP is a component-based framework with formal semantics that rely on multiparty interactions for synchronizing components. Commonly in TT implementations, tasks interact with each other through a communication medium. Our methodology transforms, depending on a user-defined task mapping, high-level BIP models where communication between components is strongly synchronized, into TT model that integrates a communication medium. Thus, only inter-task communications and components participating in such interactions are concerned by the transformation process. We also provide correctness proofs of the transformation and apply it on an industrial case study.     

基于SystemC的AADL软构件仿真代码转换技术

目前,AADL在任务关键和安全关键嵌入式领域有着良好的应用.如何在设计阶段对AADL模型进行仿真,并根据仿真结果迭代构造和精化设计模型,以尽早发现设计模型中存在的问题,保障设计模型的质量,进而减少系统开发的代价,是目前急需解决的技术挑战.SystemC是一种软硬件协同仿真的系统描述语言,由此提出了AADL软构件到Sys...     

A hardware/software prototyping system for driving assistance investigations

A holistic design and verification environment to investigate driving assistance systems is presented, with an emphasis on system-on-chip architectures for video applications. Starting with an executable specification of a driving assistance application, subsequent transformations are performed across different levels of abstraction until the final implementation is achieved. The hardware/software partitioning is facilitated through the integration of OpenCV and SystemC in the same design environment, as well as OpenCV and Linux in the run-time system. We built a rapid prototyping, FPGA-based camera system, which allows designs to be explored and evaluated in realistic conditions. Using lane departure and the corresponding performance speedup, we show that our platform reduces the design time, while improving the verification efforts.     

Telerobot-enabled HUB-CI model for collaborative lifecycle management of design and prototyping

The HUB-CI model is investigated in a telerobotic system in a client/server network to manage the lifecycle of engineering design and prototyping. The purpose of this platform is to support collaborative engineering design and proof of concept to enhance distributed team collaboration and resource utilization. The suggested platform is exemplified in two collaboration support tools and a physical prototyping platform. Structured Co-Insight Management is developed to support innovative idea exchanges and the consensus decision-making during the design process. Conflict/error detection management helps preventing conflicts and errors during the lifecycle of design and development. Physical collaboration over the network occurs when a team controls the telerobot operation during prototyping and testing in design cycles. A pilot system is implemented with a group project for the design of an electronic circuit (including both hardware and software designs). The functional assessment method is used to compare this platform to other collaborative design tools. The system presented offers unique qualitative advantages as an integrated collaboration support system.     

基于SystemC的网络处理器体系结构建模方法

随着各种新的网络业务不断出现,网络处理器得到了日益广泛的应用。文章采用基于SystemC的系统设计方法,构建一个用于网络处理器体系结构建模的平台。这个平台由一个可扩展的异构资源库和一个体系结构构造器组成。设计者只需提交配置信息表,体系结构构造器就能自动生成模型实例,得到的模型可以方便地进行细化和性能评价。这种方法能够便捷地完成各种网络处理器的体系结构建模,便于网络处理器的优化设计。     

OCCN: a NoC modeling framework for design exploration

The On-Chip Communication Network (OCCN) project provides an efficient framework, developed within SourceForge, for the specification, modeling, simulation, and design exploration of network on-chip based on an object-oriented C++ library built on top of SystemC. OCCN is shaped by our experience in developing communication architectures for different System-on-Chip. OCCN increases the productivity of developing communication driver models through the definition of a universal Application Programming Interface (API). This API provides a new design pattern that enables creation and reuse of executable transaction level models across a variety of SystemC-based environments and simulation platforms. It also addresses model portability, simulation platform independence, interoperability, and high-level performance modeling issues.     

面向服务的信息物理融合系统建模与验证

针对信息物理融合系统(CPS)中建模与验证面临的问题与挑战,基于服务组合的思想,提出一种CPS建模与验证方法。首先,综合分析已有研究成果,提出一种CPS的组成结构,包含物理世界、感知系统、信息处理系统、控制系统及时间约束。基于该结构提出CPS资源的服务分类及组成框架,并利用时间自动机理论,提出CPS物理环境建模方法、CPS原子服务建模方法及服务组合方法。最后,通过案例设计和模型检测工具Uppaal,分别对系统安全性、可达性、活性及时间约束四种类型的性质进行了相关验证。结果表明,系统通过了这些性质的验证,这也证明了面向服务的CPS建模方法的正确性。     

集成电路设计的系统级描述语言SystemC

人们提出了软件硬件协同设计的设计方法，以克服传统的将软件和硬件分开的设计方法对于SOC的设计存在的缺陷。SyStenlC是顺应这种发展趋势而产生的系统级描述语言。它是一种通过类对象扩展和基于C／C 的建模平台，支持系统级软硬件协同设计、仿真、验证、软硬件协同设计的系统级描述语言。本文介绍了系统级描述语言SySternC在集成电路设计中的应用，讨论了基于SyStemC的集成电路设计的设计流程、设计优势及其发展趋势。     

基于SystemC的嵌入式系统设计

本文提出了一种基于SystemC的嵌入式系统设计方法，SystemC是OSCI（Open SystemC Initiative)组织制定和维护的一种开放源代码的C＋＋建模平台，提供支持硬件建模和仿真的C＋＋类库及相应的仿真内核，SystemC消除了一直存在于系统级设计和硬件设计之间的语言隔阂，支持在整个嵌入式系统设计流程内使用C＋＋来统一描述硬件和软件，基于C＋＋的系统功能定义能够方便有效地映为硬件实现部分和软件实现部分，该方法同传统的设计方法相比更加灵活和有效。     

A modeling tool for simulating and design of on-chip network systems

The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip inter-connection structures. However, such networks present designers with a large number of design parameters and decisions, many of which are critical to the efficient operation of over-all on-chip system. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment that has been developed and implemented using the SystemC transaction-level modeling language. The simulation environment consists of on-chip components as well as traffic generators, which can generate various types of traffic patterns. The simulation environment has also been integrated with the NoC topology generation tool being developed in our group. A set of simulation results demonstrates the types of parameters that can affect the performance of on-chip systems, including topology variations, network latency and achievable throughput. These results also verify the modeling capabilities of the proposed simulation environment.     

Smartphone‐based object recognition with embedded machine learning intelligence for unmanned aerial vehicles

Existing artificial intelligence solutions typically operate in powerful platforms with high computational resources availability. However, a growing number of emerging use cases such as those based on unmanned aerial systems (UAS) require new solutions with embedded artificial intelligence on a highly mobile platform. This paper proposes an innovative UAS that explores machine learning (ML) capabilities in a smartphone‐based mobile platform for object detection and recognition applications. A new system framework tailored to this challenging use case is designed with a customized workflow specified. Furthermore, the design of the embedded ML leverages TensorFlow, a cutting‐edge open‐source ML framework. The prototype of the system integrates all the architectural components in a fully functional system, and it is suitable for real‐world operational environments such as seek and rescue use cases. Experimental results validate the design and prototyping of the system and demonstrate an overall improved performance compared with the state of the art in terms of a wide range of metrics.     

基于SystemC的嵌入式系统软硬件协同设计

提出了一种基于SystemC的嵌入式系统软硬件协同设计方法。SystemC是OSCI(OpenSystemCIni tiative)组织制定和维护的一种开放源代码的C 建模平台 ,提供支持硬件建模和仿真的C 类库及相应的仿真内核。通过SystemC的支持 ,该方法在整个嵌入式系统设计流程内使用C 语言来统一描述硬件和软件 ,实现软硬件的协同设计和仿真。该方法同传统的设计方法相比更加灵活和有效。     

A design flow for supporting component-based software development in multiprocessor real-time systems

Component-based software development established as an effective technique to cope with the increasing complexity of modern computing systems. In the context of real-time systems, the M-BROE framework has been recently proposed to efficiently support component-based development of real-time applications on multiprocessor platforms in the presence of shared resources. The framework relies on a two-stage approach where software components are first partitioned upon a virtual multiprocessor platform and are later integrated upon the physical platform by means of component interfaces that abstract from the internal details of the applications. This work presents a complete design flow for the M-BROE framework. Starting from a model of software components, a first method is proposed to partition applications to virtual processors and perform a synthesis of multiple component interfaces. Then, a second method is proposed to support the integration of the components by allocating virtual processors to physical processors. Both methods take resource sharing into account. Experimental results are also presented to evaluate the proposed methodology.     

Decentralized control: Status and outlook

This paper reviews state of the art in the area of decentralized networked control systems with an emphasis on event-triggered approach. The models or agents with the dynamics of linear continuous-time time-invariant state-space systems are considered. They serve for the framework for network phenomena within two basic structures. The I/O-oriented systems as well as the interaction-oriented systems with disjoint subsystems are distinguished. The focus is laid on the presentation of recent decentralized control design and co-design methods which offer effective tools to overcome specific difficulties caused mainly by network imperfections. Such side-effects include communication constraints, variable sampling, time-varying transmission delays, packet dropouts, and quantizations. Decentralized time-triggered methods are briefly discussed. The review is deals mainly with decentralized event-triggered methods. Particularly, the stabilizing controller–observer event-based controller design as well as the decentralized state controller co-design are presented within the I/O-oriented structures of large scale complex systems. The sampling instants depend in this case only on a local information offered by the local feedback loops. Minimum sampling time conditions are discussed. Special attention is focused on interaction-oriented system architecture. Model-based approach combined with event-based state feedback controller design is presented, where the event thresholds are fully decentralized. Finally, several selected open decentralized control problems are briefly offered as recent research challenges.