总线互连线电路分析的方程建立方法

针对总线互连电路,提出了一种基于电路并行结构的电路方程建立方法．该方法所建立的方程的系数矩阵均具有对称带状特性,且矩阵带宽大小等于互连线数目的两倍加一．与传统的改进节点电压方法相比,该方法显著地提高了总线互连电路分析的效率,可以被方便地运用到现有的电路模拟工具中．来提高互连电路的分析速度．     

尺度变换在互连线高阶模型仿真中的应用

Wang氏RC互连线模型的状态方程避免了矩阵求逆,传递函数采用巧妙的递归算法,使互连线的高阶仿真得以可行。但是在用MalLab做高阶仿真中,当在传递函数向状态方程转换以及用传递函数作阶跃响应和波特图时还是会发生困难。研究表明,困难来自互连线电容C值太小以及仿真阶数过高。对于高阶仿真,增大电容C值是解决发生困难的唯一途径。经过证明,增大电容C值等同于对频率进行尺度变换。电容C值扩大后,对阶跃响应图的时间轴进行同比例缩小或波特图的频率轴进行同比例扩大,即可得到原图。     

The MAGNeT Toolkit: Design, Implementation and Evaluation

The current trend in constructing high-performance computing systems is to connect a large number of machines via a fast interconnect or a large-scale network such as the Internet. This approach relies on the performance of the interconnect (or Internet) to enable fast, large-scale distributed computing. A detailed understanding of the communication traffic is required in order to optimize the operation of the entire system. Network researchers traditionally monitor traffic in the network to gain the insight necessary to optimize network operations. Recent work suggests additional insight can be obtained by also monitoring traffic at the application level. The Monitor for Application-Generated Network Traffic toolkit (MAGNeT) we describe here monitors application traffic patterns in production systems, thus enabling more highly optimized networks and interconnects for the next generation of high-performance computing systems.     

The MAGNeT Toolkit: Design,Implementation and Evaluation

The current trend in constructing high-performance computing systems is to connect a large number of machines via a fast interconnect or a large-scale network such as the Internet. This approach relies on the performance of the interconnect (or Internet) to enable fast, large-scale distributed computing. A detailed understanding of the communication traffic is required in order to optimize the operation of the entire system.Network researchers traditionally monitor traffic in the network to gain the insight necessary to optimize network operations. Recent work suggests additional insight can be obtained by also monitoring traffic at the application level.The Monitor for Application-Generated Network Traffic toolkit (MAGNeT) we describe here monitors application traffic patterns in production systems, thus enabling more highly optimized networks and interconnects for the next generation of high-performance computing systems.     

Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. In our previous work, we have proposed a new compliant interconnect technology called FlexConnect to address these concerns with compliant interconnects. An innovative cost-effective MEMS-based fabrication process is used to fabricate these compliant interconnects. Sequential lithography and electroplating processes with up to two masking steps are utilized. Utilizing the proposed fabrication process, in this paper, FlexConnects are realized at a 100-mum pitch. High-frequency modeling of the electrical parasitics of the interconnect is performed. Through finite-element-based models, the advantage of using multiple electrical paths as part of the interconnect design is shown from a thermomechanical reliability perspective. Finally, taking advantage of the MEMS-based photolithographic fabrication process, a heterogeneous combination of FlexConnects and column interconnects is proposed. This approach is shown to be an additional avenue to attain improved electrical performance without compromising mechanical performance.     

Performance evaluation and design tradeoffs of on-chip interconnect architectures

Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high-performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs. In this paper, a Network Calculus-based methodology is presented to analyze and evaluate the performance and cost metrics, such as latency and energy consumption. The 2D Mesh, Spidergong, and WK-Recursive on-chip interconnect architectures are analyzed using this methodology and results are compared with those produced using simulations. The values obtained by simulations and by analysis show similar trends in the same order of magnitude. Furthermore, WK outperforms the other on-chip interconnects in all considered metrics.     

Wafer-scale microdevice transfer/interconnect: its application in an AFM-based data-storage system

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer, and interconnect method for batch fabricating systems on chip that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 free-standing cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer (typically CMOS). Such an array is used in a highly parallel, scanning-probe-based data-storage system, which we internally call "millipede." A very high-integration density has been achieved, even for wafer-scale transfer, thanks to the interlocking nature of the interconnect structure, which provides easy alignment with an accuracy of 2 /spl mu/m. The typical integration density is 100 cantilevers/mm/sup 2/ and 300 electrical interconnects/mm/sup 2/. Note that only the cantilevers, not a chip with cantilevers, are transferred and, unlike flip-chip technology, our method preserves the device orientation, which is crucial for MEMS applications, where often the MEMS device should have access to its environment (in our case, the cantilever tips are in contact with the storage medium). After device transfer, the system is mechanically and electrically stable up to at least 500/spl deg/C, allowing post-transfer wafer processing.     

System identification and on-line robust control of a multivariable system

System identification and on-line robust control have been developed for a multi-variable system with dead times. For system identification, a modified Astrom and Hagglund' s autotuning method is applied to obtain the transfer function matrix. An accurate transfer function matrix can be obtained using the proposed method. However, if the system has noises, an accurate transfer function matrix may not be obtained even if a relay with hysteresis is used. Modelling error is unavoidable. An on-line robust control based on a stability index is proposed to improve the performance of the control system     

一种基于ASIP方法的互连IP节点设计

在研究多种互连IP节点功能的基础上,提出使用专用指令集处理器(ASIP)方法设计互连IP节点的基本功能集合,使得设计者可以实现对互连IP节点基本功能的复用,并添加定制设计以满足具体应用对互连IP节点的特定要求。ASIP方法允许设计者以编程的方式灵活地实现互连策略。DTV系统中一种互连IP节点的电路设计、仿真与综合结果验证了该设计的有效性。     

First-order performance prediction of cache memory with wafer-level 3D integration

The advantages of 3D design can be exploited by reducing the memory access time. In this article, the authors use a simulator based on analytical models to build an optimal processor-memory configuration for two designs: a graphics processor and a microprocessor. One emerging alternative approach to relieving these interconnect constraints is the use of wafer-level 3D integration, which provides a high density of high-performance, low-parasitic vertical interconnects. A wafer-level 3D design is partitionable into multiple chips connected by short vertical vias. This arrangement reduces the length of many global interconnects without introducing any logic complexity. Wafer-level 3D integration also reduces the required number of repeaters, thereby improving the area efficiency and reducing the power consumed within the interconnect network. With micron-size interwafer vias, wafer-level 3D integration allows a large memory bandwidth with little wafer area consumption. We have developed a software program that allows a first-order comparison of cache designs in 2D and 3D IC technologies. We present a first-order estimate of the performance improvements achieved by 3D implementation of cache memory, with emphasis on large caches in deep-submicron technologies.     

一种基于可观测标准型的模型降阶算法

模型降阶方法在大规模集成电路的仿真中有着广泛的应用.由于对互联网络提取寄生参数后电路的规模巨大,使用传统的电路仿真方法将会消耗大量的资源,而模型降阶使得仿真计算量显著减小的同时精度并没有多少损失.文章针对互连线网络的MNA(Modified Nodal Analysis)矩阵通常可观测性较弱的特点,提出了一种基于可观测标准型的模型降阶算法:MOROC.文中推导证明了该算法能够匹配原系统的前q个矩,且具有形式简单和容易检验稳定性的特点.并给出了应用该算法对耦合互连线的降阶建模和仿真结果.     

Incorporation of conductor losses into the stripline simulator UA‐FWLIS by using a surface impedance formulation

We use a surface impedance formulation to enable the MoM‐based full‐wave layered interconnect simulator, UA‐FWLIS, to handle conductor losses for stripline interconnects. Because these approaches are fully compatible with the previously developed analytical calculations for the reaction matrix elements, the computational efficiency of UA‐FWLIS is not affected by including conductor losses. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.     

Performance evaluation of high-speed interconnects using dense communication patterns

We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these interconnects. Our micro-benchmarks are based on dense communication patterns with different communicating partners and varying degrees of these partners. We tested our micro-benchmarks on five platforms: an IBM system of 68-node 16-way Power3, interconnected by a SP switch2; another IBM system of 264-node 4-way Power PC 604e, interconnected by an SP switch; a Compaq cluster of 128-node 4-way ES40/EV67 processor, interconnected by an Quadrics interconnect; an Intel cluster of 16-node dual-CPU Xeon, interconnected by an Quadrics interconnect; and a cluster of 22-node Sun Ultra Sparc, interconnected by an Ethernet network. Our results show many limitations of these networks including the memory contention within a node as the number of communicating processors increased and the limitations of the network interface for communication between multiple processors of different nodes.     

Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors

As transistor sizes shrink, interconnects represent an increasing bottleneck for chip designers. Several groups are developing new interconnection methods and system architectures to cope with this trend. New architectures require new methods for high-level application mapping and hardware/software codesign. We present high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessor systems-on-chip that are streamlined for one or more digital signal processing applications. That is, we seek to synthesize an application-specific interconnect topology. We show that flexible interconnect topologies utilizing low-hop communication between processors offer advantages for reduced power and latency. We show that existing multiprocessor scheduling algorithms can deadlock if the topology graph is not strongly connected, or if a constraint is imposed on the maximum number of hops allowed for communication. We detail an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock. We show that it is advantageous to perform application scheduling and interconnect synthesis jointly, and present a probabilistic scheduling/interconnect algorithm that utilizes graph isomorphism to pare the design space.     

Off-chip communication architectures for high throughput network processors

In this paper, we propose a new interconnection mechanism for network line cards. We project that the packet storage needs for the next-generation networks will be much higher. Such that the number of memory modules required to store the packets will be more than that can be directly connected to the network processor (NPU). In other words, the NPU I/O pins are limited and they do not scale well with the growing number of memory modules and processing elements employed on the network line cards. As a result, we propose to explore more suitable off-chip interconnect and communication mechanisms that will replace the existing systems and that will provide extraordinary high throughput. In particular, we investigate if the packet-switched k-ary n-cube networks can be a solution. To the best of our knowledge, this is the first time, the k-ary n-cube networks are used on a board. We investigate multiple k-ary n-cube based interconnects and include a variation of 2-ary 3-cube interconnect called the 3D-mesh. All of the k-ary n-cube interconnects include multiple, highly efficient techniques to route, switch, and control packet flows in order to minimize congestion spots and packet loss within the interconnects. We explore the tradeoffs between implementation constraints and performance. Performance results show that k-ary n-cube topologies significantly outperform the existing line card interconnects and they are able to sustain higher traffic loads. Furthermore, the 3D-mesh reaches the highest performance results of all interconnects and allows future scalability to adopt more memories and/or processors to increase the line card’s processing power.     

状态变量方程辨识Cauer热模型参数的方法

绝缘栅双极性晶体管IGBT模块热网络与可靠性密切相关。Cauer模型简单直观,为了得到模型中各元件的参数,提出一种基于现代控制理论中任意系统转换为能观标准型的一般方法,将模型的一般的状态空间表达式通过矩阵变换的方法转换为特殊的能观标准型。通过实验或仿真得到系统的传递函数,将传递函数与能观标准型进行比较,可以得到若干个方程组并求解得到所需的元件参数。通过仿真验证了该方法的可行性。     

An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs

The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a larger number of cores. Tiled CMPs offer better scalability by integrating relatively simple cores with a lightweight point-to-point interconnect. However, such interconnects make snooping impractical and, thus, require alternative solutions to cache coherence. In this article, we investigate a novel, cost-effective mechanism to support shared-memory parallel applications that forgoes hardware maintained cache coherence. This mechanism is based on the key ideas that mapping of lines to physical caches is done at the page level with OS support and that hardware supports remote cache accesses. We extend our previous work by investigating in detail the impact of system design parameters and extending the system to support multi-level cache hierarchies. Results show that the choice of implementation of multi-level cache hierarchies can have a significant impact on performance.     

Routing permutations with link-disjoint and node-disjoint paths in a class of self-routable interconnects

We consider efficiently routing permutations in a class of switch-based interconnects. Permutation is an important communication pattern in parallel and distributed computing systems. We present a generic approach to realizing arbitrary permutations in a class of unique-path, self-routable interconnects. It is well-known that this type of interconnect has low hardware cost, but can realize only a small portion of all possible permutations between its inputs and outputs in a single pass. We consider routing arbitrary permutations with link-disjoint paths and node-disjoint paths in such interconnects in a minimum number of passes. In particular, routing with node-disjoint paths has important applications in emerging optical interconnects. We employ and further expand the Latin square technique used in all-to-all personalized exchange algorithms for this class of interconnects for general permutation routing. Our implementation of permutation routing is optimal in terms of the number of passes that messages are transmitted through the network, and it is near-optimal in network transmission time for sufficiently long messages. The possibility of adopting a single-stage interconnect is also discussed.     

基于PCI-E接口的高速数字信号处理系统设计

为了满足目前实时信号处理要求,利用ADSP-TS201和Virtex4系列FPGA构建高速数字信号处理系统,采用点对点互连和紧耦合结构设计,利用FPGA自定义LVDS接口实现板级互连,通过PCI-E接口与上位机通信,具有良好的可扩展性。文章介绍了系统的结构、原理及PCB设计。     

Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

Sophisticated on-chip interconnects using packet and circuit switching techniques were recently proposed as a solution to non-scalable shared-bus schemes currently used in Systems-on-Chip (SoCs) implementation. Different interconnect architectures have been studied and adapted for SoCs to achieve high throughput, low latency and energy consumption, and efficient silicon area. Recently, a new on-chip interconnect architecture by adapting the WK-recursive network topology structure has been introduced for SoCs. This paper analyses and compares the energy consumption and the area requirements of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, Fat-Tree and Butterfly Fat-Tree. We investigated the effects of load and traffic models and the obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements. In these results, WK-recursive interconnect generally has a higher energy consumption and silicon area requirements in heavy traffic load.