通用电路分析程序SPICE-Ⅱ中的MOS场效应管模型(二)

<正> Ⅳ.MOS3模型与MOS2解析模型不同,MOS3采用半经验公式描述器件中的二阶效应,包括: (1)短沟道和狭沟道效应对阈值电压的影响; (2)静电反馈对阈值电压的影响; (3)热电子效应对迁移率的影响;     

随机栅长变化引起纳米MOSFET失配模型

随着CMOS技术进入纳米工艺,随机栅长变化成为影响集成电路性能和成品率最重要因素之一.文中分析并验证了纳米MOS器件随机栅长变化导致电流增益因子与阈值电压的之间的相关性及失配解析关系式,并以此为基础,结合偏差传递理论实现了22 nm工艺MOSFET电流失配模型.仿真实验结果表明,该模型揭示了短沟道效应导致的器件阈值电压变化改变了载流子有效迁移率,进而影响电流增益因子及器件电流的规律,精确地估计了随机栅长变化导致的电气参数统计变化特性.     

VLSI晶体管级时延模拟方法

提出了一种新的晶体管级时延模拟方法，为了保证模拟的精度，综合考虑了存在于短沟道晶体管中的短路电流、输入／输出耦合电容和载流子速度饱和等效应对MOSFET晶体管沟道电流的影响，针对经典的ALPHA沟道电流分析模型（Alpha-Power-Law）进行了改良，以达到精确计算沟道电流的目的．该方法通过改良的节点分析方程（MNA）计算逻辑门的输出波形，以获得逻辑门的时间延迟和跳变时间．所开发的晶体管级时延模拟器性能优越，当逻辑门中某一晶体管的一个参数（如沟道长度、宽度或阈值电压％0）改变后，模拟器可以快速地计算出新的逻辑门输出波形．基于BSIM370nm工艺模型，采用HSPICE软件的模拟结果来验证该方法的效率与精确性．实验结果表明：该方法模拟效率高，模拟一个逻辑门平均仅需1．0ms；模拟精度高，在所有测试电路时延模拟结果中，最大误差仅为5．04％，平均误差为2．68％．     

短沟道SOI中的阈值电压下降问题的研究

运用电荷分享模型推导出背界面处于耗尽状态的单栅和双栅薄膜SOIMOSFET中短沟道效应引起的闽值电压下降的理论模型。利用MatLab进行了数值模拟计算．并比较了单栅和双栅器件的结果。同时分析了沟道区掺杂浓度、硅膜厚度、栅氧化层厚度对阈值电压下降的影响。结果表明．薄膜器件有利于减小短沟道效应．而双栅器件短沟道效应比单栅器件减小4倍。另外．对于薄膜器件来说,改变器件结构要比改变器件参数对短沟道效应的抑制作用好得多。     

一种全CMOS低功耗基准电压源的设计

基于MOSFET亚阈值的特性,通过两个MOSFET阈值电压差与热电压VT相互补偿的原理,提出了一种全CMOS基准电压源电路。与传统带隙基准电路相比,该电路采用全CMOS器件,无需电阻和传统分立电容,具有电路结构简单、功耗低、温度系数小和面积小的特点。通过对电路的理论分析,采用SMIC 0.18μm CMOS工艺模型,利用Cadence工具对电路进行仿真验证,在电源电压为1.8 V的条件下,输出电压为364.3 mV(T=27℃),温度系数为6.7 ppm/℃(-40℃~+125℃),电源抑制比达到-68 dB@10 kHz,功耗为1.3μW。     

电介质击穿对MOSFET器件漏电流的影响

栅电介质击穿是MOSFET器件工作中主要的失效模式之一。由击穿而引起的栅泄漏不仅是电损耗增加的问题,而且对漏电流造成很大的影响。采用最新工艺制成的超薄栅电介质,把由击穿产生的漏电流作为因击穿点的扩展而损伤的沟道电流的一部分。制作栅氧厚度为2.2nm和3.5nm、不同沟道宽度的器件,使用专门的装置给器件施加应力,用统计方法研究晶体管性能的退化。分析表明,使漏电流退化的损伤半径大约在1.4μm-1.8μm之间。     

基于TCAD的低压沟槽MOSEFT栅漏电荷的研究

对于低压功率沟槽MOSFET的开关性能,栅-漏电荷Qgd是一个重要的参数。本文利用数值模拟软件TCAD（器件与工艺计算机辅助设计）,研究了氧化层厚度、沟道杂质分布、外延层杂质浓度及沟槽深度等参数对功率沟槽MOSFET的栅-漏电容Cgd的影响以及栅-漏电荷Qgd在开关过程中的变化,指出了在工艺设计上减小栅-漏电容Cgd,降低器件优值,提高开关性能的途径。     

一个简单的65nm MOSFET失配模型

MOSFET的精确匹配对模拟和混合集成电路的性能至关重要,随着器件特征尺寸减小至纳米,将MOSFET失配模型进行改良以适应新工艺显得十分迫切.文中应用改进的AIPHA律平均漏电流模型拟合65 nm器件的HSPICE仿真数据,并提取了相关工艺参数,该模型与BSIM4模型数据相比平均相对误差为1.70%,相对标准差8.26%;再利用该模型并结合偏差传递公式实现了一个简单的65nm工艺MOS器件电流失配标准差计算模型.实验结果显示,该模型与HSPICE蒙特-卡罗仿真数据相比平均相对误差为7.69%,相对标准差为10.49%.这表明文中模型简单、有效,又能保证精度.     

MEMS器件热致封装效应的解析建模研究

由封装结构热失配引入的结构变形和应力将对MEMS器件性能产生显著影响,即热致封装效应.基于单元库法思想构建了封装后MEMS器件的解析模型.新建锚区、芯片、封装基板等标准单元,利用节点分析法描述了各结构单元间的热弹性耦合行为,以此作为封装效应评估的基础.利用该模型计算了热致封装效应对常规芯片粘接封装的双端固支梁器件主要性能参数的影响.     

MOSFET寄生参数对LLC谐振变换器性能影响研究

针对MOSFET寄生参数对LLC谐振电路性能的影响,首先对MOSFET的寄生电容进行等效分析,基于该等效模型,分析在LLC谐振变换电路中,寄生参数的存在对电路各个阶段过程的影响;接着对由于寄生参数引起的非线性特征,基于Angelov模型进行建模,并对该模型在直流电路中的影响进行分析。最后在MATLAB下建立了LLC谐振电路模型,在仿真模型中考虑了寄生参数的影响。仿真结果表明,建立的等效模型可以较好地反映MOSFET器件的工作特点;同时,由于寄生参数的存在, LLC谐振电路的输出增益和谐振频率都会受到影响,其中尤以对谐振频率的影响较大。     

纳米MOSFET寄生电阻模型分析

随着器件尺寸的缩小,寄生电阻对器件性能的影响不可忽视,为准确预测器件的寄生电阻并了解器件参数对寄生电阻的影响,需要有准确的寄生电阻模型。该文分析了短沟道寄生电阻模型．研究了短沟道寄生电阻模型在栅压较小时与模拟结果存在较大误差的原因,并对模型进行了改进。最后分析了器件参数对寄生电阻的影响,提出未来减小寄生电阻需要和可能采取的措施。     

An efficient PSP-based model for optimized cross-coupled MOSFETs in voltage controlled oscillator

This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design.     

A quantum-confinement model for surrounding-gate MOSFETS from subthreshold to strong-inversion regions

A new analytical model is developed for quantum-confinement effects of short channel surroundinggate MOSFETs.The eigenenergies and wavefunctions are obtained by solving Schrdinger’s equation with an accurate potential energy distribution.The potential energy distribution is derived from the solution of Poisson’s equation,which contains both depletion charge and free charge.The eigenenergies obtained from our model are compared with other two quantum-confinement models,which use flat-well approximation and parabola-well approximation as the potential energy distributions,respectively.And we point out the relationship between the eigenenergies and the potential energy distribution for the first time.Based on this model,the electron density with quantum confinement effects are derived,and threshold voltage is defined based on average electron density.After considering quantum confinement effects,the electron density becomes smaller while the threshold voltage becomes larger.The results show that this model is applicable from the subthreshold region to the stronginversion region in different channel doping conditions.     

One-dimensional axial simulation of electric double layer overlap effects in devices combining micro- and nanochannels

This paper presents a numerical steady-state model of ion transport in micro- and nanofluidic devices with widely varying geometric scale, such as transitions between micro- and nanochannels. Finite element or finite volume simulation of such problems is challenging, due to the number of elements needed to produce a satisfactory mesh. Here, only the lengthwise channel dimension is meshed; standard analytical approximations are used to incorporate cross-channel properties. Singularly perturbed cases are built up by continuation. The method is shown to reproduce our previously reported measurements of electric double-layer effects on conductivity, ion concentration, and ion enhancement and depletion. Comparison with 2-D simulations reported in the literature shows that effects on accuracy due to the 1-D approximation are small. The model incorporates analytical models of surface charge density taken from the literature. This enables predictive simulation with reasonable accuracy using published parameter values, or these values may be tuned based on experiment to give improved results. Use of the model for iterative design and parameter estimation is demonstrated.     

Modeling,verification and comparison of short-channel double gate and gate-all-around MOSFETs

Models for short-channel DG and GAA MOSFETs are presented. In the subthreshold regime, the electrostatics of the device is dominated by the capacitive coupling between the electrodes, which is analyzed by conformal mapping techniques. In the strong inversion regime, the device behavior is dominated by the inversion charge, allowing a 1D analysis. The models are verified by comparison with numerical device simulations. The electrostatic properties of the DG and GAA are compared, demonstrating the superior short-channel behavior of the GAA design.     

Phase detection based range estimation with a dual-band robust Chinese remainder theorem

Range estimation with multifrequency phases is a common practice in localization systems.The challenge of this method is the phase ambiguity.Some Chinese remainder theorem(CRT)based phase unwrapping algorithms have been proposed to solve the problem,where the wavelengths of the multifrequency signals need to be pair-wisely co-prime after they are divided by their greatest common divisor(gcd).This condition may limit the application in practice.In this paper,a novel way based on a dual-band robust CRT is presented to reconstruct the distance from dual-band wrapped phases,where the pair-wisely co-prime condition is not necessarily needed.As more wrapped phases are involved to reconstruct the distance,the method can significantly enlarge the reconstruction range compared to the single band solution.     

纳米MOSFET寄生电阻模型分析

随着器件尺寸的缩小,寄生电阻对器件性能的影响不可忽视,为准确预测器件的寄生电阻并了解器件参数对寄生电阻的影响,需要有准确的寄生电阻模型。该文分析了短沟道寄生电阻模型,研究了短沟道寄生电阻模型在栅压较小时与模拟结果存在较大误差的原因,并对模型进行了改进。最后分析了器件参数对寄生电阻的影响,提出未来减小寄生电阻需要和可能采取的措施。     

Multilevel 2-D Bar Codes: Toward High-Capacity Storage Modules for Multimedia Security and Management

In this paper, we deal with the design of high-rate multilevel 2-D bar codes for the print-and-scan channel. First, we introduce a framework for evaluating the performance limits of these codes by studying an intersymbol-interference (ISI)-free, synchronous, and noiseless print-and-scan channel, where the input and output alphabets are finite and the printer device uses halftoning to simulate multiple gray levels. Second, we present a new model for the print-and-scan channel specifically adapted to the problem of communications via multilevel 2-D bar codes. This model, inspired by our experimental work, assumes perfect synchronization and absence of ISI, but independence between the channel input and the noise is not assumed. We adapt the theory of multilevel coding with multistage decoding (MLC/MSD) to the print-and-scan channel. Finally, we present experimental results confirming the utility of our channel model, and showing that multilevel 2-D bar codes using MLC/MSD can reliably achieve the high-capacity storage requirements of many multimedia security and management applications     

An improved constant coefficient multiplication algorithm based on cascaded adder graph

In many digital signal processing algorithms,e.g.,digital filters,the multiplier coefficients are constant.Hence,it is possible to implement the multiplier using shifts,adders,and subtracters.In this work a new algorithm of constant coefficient multiplication with few adders and registers is proposed.This approach is based on cascaded adder graph.In this paper all cascaded adder graph structures for any integer can be derived,and the analytical method for the number of register and adder occupation is given.Through comparison of occupied resources,the optimal adder graph can be obtained.Finally,comparing with previous optimal algorithms,a design example for finite impulse response(FIR) filter confirms the validity and good engineering practicability of this algorithm.     

Development of a methodology for the extraction of BSIM3v3.2.2 parameters of Ge-channel MOSFETs and estimation of analog circuit performance

We have developed an algorithm which utilizes model equations for MOSFETs to extract BSIM3v3.2.2 MOSFET model parameters of Ge-channel transistors. The model represents the entire transfer characteristics from sub-threshold to strong inversion regions and the output characteristics from linear to saturation regions thus capturing all the operating bias conditions of gate to source voltage V_GS and drain to source voltage V_DS. For extraction of various BSIM parameters, the model equations are fitted with reported experimental characteristics, and some with TCAD simulation data of Ge MOSFETs for various geometrical dimensions over a wide range of bias conditions. The algorithm used for extracting BSIM3V3.2.2 parameters by fitting BSIM3v3.2.2 model equations with experimental or simulation data is written in MATLAB code. The extracted BSIM model parameters are employed in ADS circuit simulator to reproduce the transfer characteristics of Ge MOSFETs with the same channel length and channel width of 80 nm for both high and low body bias conditions. The characteristics obtained from ADS match well with those obtained from TCAD simulation using SILVACOATLAS thereby ensuring the accuracy of our extraction methodology. The extracted set of BSIM3V3.2.2 parameters is used to generate transfer and output characteristics of Ge channel pMOSFETs at channel length of 70 nm. The extracted value of threshold voltage, bulk mobility and saturation velocity are −0.2 V, 0.18 m²/V.s and 1.2 × 10⁶ m/s, respectively. Our study reveals that various device parameters such as transconductance, intrinsic voltage gain, and cut-off frequency show a maximum value of 677 μS/μm, 2.7, and 63 GHz, respectively.