Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

A low-power scan driver employing IZO TFTs including an AC–DC type output module

This paper presents a low-power and simple scan driver with a new output module called as AC–DC type output module. 46 stages of the scan driver are fabricated by integrating In–Zn–O Thin-film transistors (IZO TFTs) with back channel etch (BCE) structure on the glass substrate. Under 100 hours’ test, it is shown that the voltage fluctuation of the output signal can be well suppressed by the proposed AC–DC type output module up to the whole 46 stages. The power consumption can be obviously reduced by using the AC–DC type output module compared with the conventional AC–AC type output module. It is measured that the power consumption of one stage for the proposed scan driver with AC–DC type output module at the clock frequency of 16.7 kHz is 170 μW, as well as 393 μW for the proposed scan driver with the conventional AC–AC type output module. It is shown from the simulation results that there is a good tradeoff between the power consumption and the rising time for the proposed AC–DC type output module compared with AC–AC type output module and DC–DC type output module.     

A magnetoelectric energy harvester and management circuit for wireless sensor network

This paper presents an electromagnetic energy harvesting scheme by using a composite magnetoelectric (ME) transducer and a power management circuit. In the transducer, the vibrating wave induced from the magnetostrictive Terfenol-D plate in dynamic magnetic field is converged by using an ultrasonic horn. Consequently more vibrating energy can be converted into electricity by the piezoelectric element. A switching capacitor network for storing electricity is developed. The output of the transducer charges the storage capacitors in parallel until the voltage across the capacitors arrives at the threshold, and then the capacitors are automatically switched to being in series. More capacitors can be employed in the capacitor network to further raise the output voltage in discharging. For the weak magnetic field environment, an active magnetic generator and a magnetic coil antenna under ground are used for producing an ac magnetic field of 0.2–1 Oe at a distance of 25–50 m. In combination with the supply management circuit, the electromagnetic energy harvester with a rather weak power output (about 20 μW) under an ac magnetic field of 1 Oe can supply power for wireless sensor nodes with power consumption of 75 mW at a duration of 620 ms.     

Design of high speed gate driver employing IZO TFTs

This paper presents a new bi-side gate driver integrated by indium-zinc-oxide thin film transistors (IZO TFTs). Our optimized operate method can achieve high speed performance by employing a lower duty ratio (25%) CK2 with its pulse located in the middle of the pulse of CK2L to fully use the bootstrapped high voltage of node Q. In addition, the size of devices is optimized by calculation and simulation, and the function of the proposed gate driver is predicted by the circuit simulation. Furthermore, the proposed gate driver with 20 stages is fabricated by the IZO TFTs process. It is shown that a 2.6 μs width pulse with good noise-suppressed characteristic can be successfully output at the condition of R_load = 6 kΩ and C_load = 150 pF. The power consumption of the proposed gate driver with 20 stages is measured as 1 mW. Hence, the proposed gate driver may be applied to the display of 4K resolution (4096 × 2160) at a frame rate of 120 Hz. Moreover, there is a good stability for the proposed gate driver under 48 h operation.     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Improvement of picture quality of high Xe content plasma display panels based on facing discharge suppression

This paper presents a waveform for driving a high-resolution plasma display panel (PDP) which uses a gas mixture of high Xe content. To prevent degradation of picture quality due to unstable discharges between two facing electrodes, the common electrode was biased at a negative voltage during the set-up period, and the data electrode was biased at a positive voltage during the sustain period. A pre-reset pulse was used before the first reset to reduce the reset voltage and to form a proper wall charge state for sustain discharges. This waveform could drive a 15% Xe 42 in. XGA (1024 × 768) PDP with the single-scan method. The measured black luminescence, peak luminescence, and contrast ratio were 0.45, 1490 cd/m², and 3310:1, respectively. The measured margin of the sustain voltage was better than ±10 V.     

Novel voltage programming n-channel TFT pixel circuit for low power and high performance AMOLED displays

This paper proposes a novel pixel circuit for high resolution, high frame rate, and low power AMOLED displays that is implemented with one driving n-channel TFT, six switching n-channel poly-Si TFTs, and a storage capacitor. The proposed pixel circuit adopts the voltage programming scheme for threshold voltage compensation. Because the whole line time is in use only for charging the data voltage, this pixel circuit is applicable to high resolution and frame rate displays. In addition, it compensates voltage variation of OLEDs and voltage drop of supply lines at lower power consumption. On the average, the non-uniformity of a proposed circuit is reduced to 2.5%, compared to 7.1% of the previous one at a 240 Hz full-HD display. On the other hand, the compensation voltage error, which is caused by feed-through and charge injection noises from falling control signals of switching TFTs, is much less in the proposed scheme than in the previous 5T2C structure. The average error of the proposed circuit is reduced to 0.18 V, compared to 0.75 V of the previous one. The initialization power consumption of the 7T1C circuit is reduced to 98 mW, compared to 530 mW of the 5T2C circuit and the average dynamic power saving ratio of data drivers is estimated in the 7T1C pixel as 98.7% over the 5T2C one for 24 test images.     

An ergonomic study on the optimal gear ratio for a multi-speed bicycle

With respect to human performance and power efficiency, the gear system in typical multi-speed bicycles is often biased and redundant. A preliminary user survey in this study reveals that the average utilization of each shift for a multi-speed gear system is less than 40%. This study attempts to measure the optimal pedaling rates for given power output levels as well as design the optimal number of gears and the corresponding gear ratios.Heart rate, ratings of perceived exertion and electromyogram of quadriceps femoris for five male subjects are measured at three different power output levels (40, 80 and 120 W) and four different pedaling rate levels (40, 60, 80 and 100 rpm). Various riding conditions including slope gradient and cruising velocity are also converted to the equivalent power output level.The optimal pedaling rates for the given power output are 40 rpm for 40 W power output level, 40 – 60 rpm for 80 and 120 W power output levels. By using a heuristic rule which finds the least number of gears and the most efficient gear ratio under the given physiological condition, a four speed gear system with the ratio of 0.26–0.38, 0.38–0.53, 0.53–0.7 and 0.7–1.0 is recommended as the most efficient gear system. Based on the optimal gear ratio suggested in this study, an ergonomic gear system using a novel/unique type of planet gear sets (US patent No. 5 378 201) is developed.Relevance to industryA bicycle's gear system is frequently designed without ergonomic expertise in terms of performance and efficiency. This study provides guidelines, design specifications, and performance measures to design an efficient bicycle gear system. This study also contributes valuable finding regarding the optimal performance during bicycle riding, thereby facilitating the efficiency and effectiveness of human exercise using a bicycle.     

Development of wireless compressive/relaxation-stress measurement system integrated with pressure-sensitive carbon black-filled silicone rubber-based sensors

In order to detect the installation compressive stress and monitor the stress relaxation between two bending surfaces on a defensive furnishment, a wireless compressive-stress/relaxation-stress measurement system based on pressure-sensitive sensors is developed. The flexible pressure-sensitive stress sensor array is fabricated by using carbon black-filled silicone rubber-based composite. The wireless stress measurement system integrated with this sensor array is tested with compressive stress in the range from 0 MPa to 3 MPa for performance evaluation. Experimental results indicate that the fractional change in electrical resistance of the pressure-sensitive stress sensor changes linearly and reversibly with the compressive stress, and its fractional change goes up to 355% under uniaxial compression; the change rate of the electrical resistance can track the relaxation stress and give out a credible measurement in the process of stress relaxation. The relationship between input (compressive stress) and output (the fractional change in electrical resistance) of the pressure-sensitive sensor is ΔR/R₀ = σ × 1.2 MPa^?1. The wireless compressive stress measurement system can be used to achieve sensitivity of 1.33 V/MPa to the stress at stress resolution of 920.3 Pa. The newly developed wireless stress measurement system integrated with pressure-sensitive carbon black-filled silicone rubber-based sensors has advantages such as high sensitivity to stress, high stress resolution, simple circuit and low energy consumption.     

Ultra high performance planar InGaAs PIN photodiodes for high speed optical fiber communication

This paper reports a front-illuminated planar InGaAs PIN photodiode with very low dark current, very low capacitance and very high responsivity on S-doped InP substrate. The presented device which has a thick absorption layer of 2.92 μm and a photosensitive area 73 μm in diameter exhibited the high performance of a very low capacitance of 0.47 pF, a very low dark current of 0.041 nA, a very high responsivity of 0.99 A/W (79% quantum efficiency) at λ = 1.55 μm, the 3 dB bandwidths of 6.89 GHz (−5 V), 7.48 GHz (−12 V) for bare chips and 4.48 GHz (−5 V), 5.02 GHz (−12 V) for the devices packaged in TO can, respectively. Furthermore, the developed PIN photodiodes possess high breakdown voltage of less than −25 V.     

A high-accuracy,high-speed interface circuit for differential-capacitance transducer

A novel high-accuracy and high-speed interface circuit based on lock-in detector is presented for differential-capacitance transducer. In the interface, the feedback capacitance rather than feedback resistance is used in the current detector to reduce the noise due to large resistance. Capacitor–array circuit proposed makes possible to cover a wide range of capacitance changes by choosing feedback capacitor close to the measurand, which results in transfer coefficient of the current sensing circuit about −1. A precision full-wave rectifier based on phase-sensitive-detector (PSD) incorporated in demodulator eliminates the effect due to threshold voltage of diode to improve the accuracy and suppress noise. A second-order low-pass filter is incorporated in demodulator, which allows high-speed and high-accuracy interface for differential-capacitance transducers. Moreover, the circuit is immune to parasitic capacitance, resistances and exciting source. It is capable of detecting the capacitance change as small as 0.005% of the total capacitance up to 16 pF with the speed higher than 5 ksps. A capacitance diaphragm pressure transducer and a standard pressure source (RUSCA 2465 piston gauge) are connected to the circuit to confirm the analysis.     

Darwin: A neuromorphic hardware co-processor based on spiking neural networks

Spiking Neural Network (SNN) is a type of biologically-inspired neural networks that perform information processing based on discrete-time spikes, different from traditional Artificial Neural Network (ANN). Hardware implementation of SNNs is necessary for achieving high-performance and low-power. We present the Darwin Neural Processing Unit (NPU), a highly-configurable neuromorphic hardware co-processor based on SNN implemented with digital logic, supporting a configurable number of neurons, synapses and synaptic delays. The Darwin NPU was fabricated by standard 180 nm CMOS technology with area size of 5 × 5 mm² and 70 MHz clock frequency at the worst case. It consumes 0.84 mW/MHz with 1.8 V power supply for typical applications. Two prototype applications are used to demonstrate the performance and efficiency of the Darwin NPU.     

A 24-h forecast of ozone peaks and exceedance levels using neural classifiers and weather predictions

A neural network combined to a neural classifier is used in a real time forecasting of hourly maximum ozone in the centre of France, in an urban atmosphere. This neural model is based on the MultiLayer Perceptron (MLP) structure. The inputs of the statistical network are model output statistics of the weather predictions from the French National Weather Service. These predicted meteorological parameters are very easily available through an air quality network. The lead time used in this forecasting is (t + 24) h. Efforts are related to a regularisation method which is based on a Bayesian Information Criterion-like and to the determination of a confidence interval of forecasting. We offer a statistical validation between various statistical models and a deterministic chemistry-transport model. In this experiment, with the final neural network, the ozone peaks are fairly well predicted (in terms of global fit), with an Agreement Index = 92%, the Mean Absolute Error = the Root Mean Square Error = 15 μg m⁻³ and the Mean Bias Error = 5 μg m⁻³, where the European threshold of the hourly ozone is 180 μg m⁻³.To improve the performance of this exceedance forecasting, instead of the previous model, we use a neural classifier with a sigmoid function in the output layer. The output of the network ranges from [0,1] and can be interpreted as the probability of exceedance of the threshold. This model is compared to a classical logistic regression. With this neural classifier, the Success Index of forecasting is 78% whereas it is from 65% to 72% with the classical MLPs. During the validation phase, in the Summer of 2003, six ozone peaks above the threshold were detected. They actually were seven.Finally, the model called NEUROZONE is now used in real time. New data will be introduced in the training data each year, at the end of September. The network will be re-trained and new regression parameters estimated. So, one of the main difficulties in the training phase – namely the low frequency of ozone peaks above the threshold in this region – will be solved.     

Development of a wide-tuning range and high Q variable capacitor using metal-based surface micromachining process

This study aims to improve the tuning range and quality-factor (Q) of micro variable capacitors for wireless communication applications. A suspending 0.5 μm-thick gold thin-plate with two-gap structure in one-to-three ratio of spacing is designed for the maximization of tuning range. To enhance effectively the flexural rigidity of top metal-plate and improve further the tuning range of the varactor, a double-cross-type microstructure with two vertical fixed-fixed beam springs and four horizontal fixed-guided cantilever beams is introduced. Besides, a glass substrate (Corning 7740) was used to reduce substantially the power dissipation and improve the Q-factor of variable capacitor. The new glass-based double-cross-type micro variable capacitor has demonstrated many superior performances, including the wide-tuning range (2100%, at 1.0 MHz with 6.0 V), the moderate capacitance (0.56 pF, at 2.4 GHz and without DC bias), 6.5 V pull-in voltage, and the high Q-factor (40.6, at 2.4 GHz). These characteristics approximately match with the theoretical derivation or simulated results from Agilent-ADS, Ansoft-HFSS, and IntelliSuite software.     

Efficient multicast schemes for 3-D Networks-on-Chip

3-D Networks-on-Chip (NoCs) have been proposed as a potent solution to address both the interconnection and design complexity problems facing future System-on-Chip (SoC) designs. In this paper, two topology-aware multicast routing algorithms, Multicasting XYZ (MXYZ) and Alternative XYZ (AL + XYZ) algorithms in supporting of 3-D NoC are proposed. In essence, MXYZ is a simple dimension order multicast routing algorithm that targets 3-D NoC systems built upon regular topologies. To support multicast routing in irregular regions, AL + XYZ can be applied, where an alternative output channel is sought to forward/replicate the packets whenever the output channel determined by MXYZ is not available. To evaluate the performance of MXYZ and AL + XYZ, extensive experiments have been conducted by comparing MXYZ and AL + XYZ against a path-based multicast routing algorithm and an irregular region oriented multiple unicast routing algorithm, respectively. The experimental results confirm that the proposed MXYZ and AL + XYZ schemes, respectively, have lower latency and power consumption than the other two routing algorithms, meriting the two proposed algorithms to be more suitable for supporting multicasting in 3-D NoC systems. In addition, the hardware implementation cost of AL + XYZ is shown to be quite modest.     

Passive single chip wireless microwave pressure sensor

A novel micromachined passive wireless pressure sensor is presented. The device consists of a tuned circuit operating at 10 GHz fabricated on to a SiO₂ membrane, supported on a silicon wafer. A pressure difference across the membrane causes it to deflect so that an antenna circuit detunes. The circuit is remotely interrogated to read off the sensor data wirelessly. The chip area is 5 mm × 4 mm and the membrane area is 2 mm² with a thickness of 4 μm. Two on-chip passive resonant circuits were investigated: a meandered dipole and a zigzag antenna. Both have a physical length of 4.25 mm. The sensors show a shift in their resonant frequency in response to changing pressure of 10.28–10.27 GHz for the meandered dipole, and 9.61–9.58 GHz for the zigzag antenna. The sensitivities of the meandered dipole and zigzag sensors are 12.5 kHz/mbar and 16 kHz/mbar respectively.     

Taguchi-fuzzy multi output optimization (MOO) in high speed CNC turning of AISI P-20 tool steel

This paper presents the application of Taguchi method with logical fuzzy reasoning for multiple output optimization of high speed CNC turning of AISI P-20 tool steel using TiN coated tungsten carbide coatings. The machining parameters (cutting speed, feed rate, depth of cut, nose radius and cutting environment) are optimized with considerations of the multiple performance measures (surface roughness, tool life, cutting force and power consumption). Taguchi’s concepts of orthogonal arrays, signal to noise (S/N) ratio, ANOVA have been fuzzified to optimize the high speed CNC turning process parameters through a single comprehensive output measure (COM). The result analysis shows that cutting speed of 160 m/min, nose radius of 0.8 mm, feed of 0.1 mm/rev, depth of cut of 0.2 mm and the cryogenic environment are the most favorable cutting parameters for high speed CNC turning of AISI P-20 tool steel.     

Design of embedded TCAM based longest prefix match search engine

The content addressable memory (CAM) based solutions are very useful in network applications due to its high speed parallel search mechanism. This paper presents a novel Ternary CAM (TCAM) based NAND Pseudo CMOS–Longest Prefix Match (NPC–LPM) search engine. The proposed system provides a simple hardware based solution using novel 11T TCAM cell structures and NPC word line technique, for network routers. The experiments were performed on 256 × 128 NPC–LPM system under 0.13 μm technology. The simulation result shows that the proposed design provides low power dissipation of 5.78 mW and high search speed of 315 MSearches/s under 1.3 V supply voltage. The presented NPC–LPM system meets the speed requirement of Optical Carrier (OC) 3072 with line-rate of 160 Gb/s in Ethernet networking and IPv6 protocol. The experimental results also show that the proposed system improves power-performance by 65%.     

High‐reliability gate driver circuit to prevent ripple voltage

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.