A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs

This paper proposes an oxide TFT DC-type shift register that consists of eleven TFTs and one bootstrapping capacitor. The proposed circuit connects drain nodes of large size pull-up TFTs of output drivers to positive supply voltage instead of alternating clock signals for low power consumption. In addition, a robust internal inverter capable of maintaining the high voltage level of the output over the large positive threshold voltage shift by bootstrapping is implemented. For a 120 Hz Full-HD display, the SPICE simulation estimates the clock power consumption of the proposed DC-type circuit as 0.56 mW at 32 shift registers and ensures the robust operation over the wide range of threshold voltage shift from −4 V to 10 V.     

Novel voltage programming n-channel TFT pixel circuit for low power and high performance AMOLED displays

This paper proposes a novel pixel circuit for high resolution, high frame rate, and low power AMOLED displays that is implemented with one driving n-channel TFT, six switching n-channel poly-Si TFTs, and a storage capacitor. The proposed pixel circuit adopts the voltage programming scheme for threshold voltage compensation. Because the whole line time is in use only for charging the data voltage, this pixel circuit is applicable to high resolution and frame rate displays. In addition, it compensates voltage variation of OLEDs and voltage drop of supply lines at lower power consumption. On the average, the non-uniformity of a proposed circuit is reduced to 2.5%, compared to 7.1% of the previous one at a 240 Hz full-HD display. On the other hand, the compensation voltage error, which is caused by feed-through and charge injection noises from falling control signals of switching TFTs, is much less in the proposed scheme than in the previous 5T2C structure. The average error of the proposed circuit is reduced to 0.18 V, compared to 0.75 V of the previous one. The initialization power consumption of the 7T1C circuit is reduced to 98 mW, compared to 530 mW of the 5T2C circuit and the average dynamic power saving ratio of data drivers is estimated in the 7T1C pixel as 98.7% over the 5T2C one for 24 test images.     

Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals

Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Amorphous‐oxide TFT backplane for large‐sized AMOLED TVs

Abstract— Amorphous‐oxide thin‐film‐transistor (TFT) arrays have been developed as TFT backplanes for large‐sized active‐matrix organic light‐emitting‐diode (AMOLED) displays. An amorphous‐IGZO (indium gallium zinc oxide) bottom‐gate TFT with an etch‐stop layer (ESL) delivered excel lent electrical performance with a field‐effect mobility of 21 cm²/V‐sec, an on/off ratio of >10⁸, and a subthreshold slope (SS) of 0.29 V/dec. Also, a new pixel circuit for AMOLED displays based on amorphous‐oxide semiconductor TFTs is proposed. The circuit consists of four switching TFTs and one driving TFT. The circuit simulation results showed that the new pixel circuit has better performance than conventional threshold‐voltage (VTH) compensation pixel circuits, especially in the negative state. A full‐color 19‐in. AMOLED display with the new pixel circuit was fabricated, and the pixel circuit operation was verified in a 19‐in. AMOLED display. The AMOLED display with a‐IGZO TFT array is promising for large‐sized TV because a‐IGZO TFTs can provide a large‐sized backplane with excellent uniformity and device reliability.     

Clocked control scheme of separating TFTs for a node‐sharing LTPS TFT shift register with large number of outputs

This paper proposes the node‐sharing low‐temperature poly‐silicon (LTPS) thin‐film transistor (TFT) shift register with the clocked control scheme that completely turns separating TFTs off during the bootstrapping period to compensate for internal resistive and capacitive loads. The fluctuation is also addressed by adding pull‐down TFTs or raising the low level of the control signal.     

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel have been developed. The data drivers include shift registers, sample‐and‐hold circuits, and operational amplifiers, and drive LCD panels using a line‐at‐a‐time addressing method. To reduce the power consumption of the shift register, a dot‐clock control circuit has been developed. Using this circuit, the power consumption of the shift register has been reduced to 36% of that of conventional circuits. To cancel the offset voltage generated by the operational amplifier, an offset cancellation circuit for low‐temperature poly‐Si TFTs has been developed. This circuit is also able to avoid any unstable operation of the operational amplifier. Using this circuit, the offset voltage has been reduced to one‐third of the value without using the offset cancellation circuit. These data drivers have been connected to an LCD panel and have realized an SVGA display on a 12.1‐in. a‐Si TFT‐LCD panel.     

PECVD‐based nanocrystalline‐silicon TFT backplanes for large‐sized AMOLED displays

Abstract— A 14.1‐in. AMOLED display using nanocrystalline silicon (nc‐Si) TFTs has been developed. Nanocrystalline silicon was deposited using conventional 13.56‐MHz plasma‐enhanced chemical vapor deposition (PECVD). Detailed thin‐film characterization of nc‐Si films was followed by development of nc‐Si TFTs, which demonstrate a field‐effect mobility of about 0.6–1.0 cm²/V‐sec. The nc‐Si TFTs show no significant shift in threshold voltage when over 700 hours of constant current stress is applied, indicating a stable TFT backplane. The nc‐Si TFTs were successfully integrated into a 14.1‐in. AMOLED display. The display shows no significant current decrease in the driving TFT of the 2T‐1cap circuit because the TFTs are highly stable. In addition to the improved lifetime of AMOLED displays, the development of nc‐Si TFTs using a conventional 13.56‐MHz PECVD system offers considerable cost advantages over other laser and non‐laser polysilicon‐TFT technologies for large‐sized AMOLEDs.     

Novel a‐Si:H TFT pixel circuit for electrically stable top‐anode light‐emitting AMOLEDs

Abstract— A novel pixel circuit for electrically stable AMOLEDs with an a‐Si:H TFT backplane and top‐anode organic light‐emitting diode is reported. The proposed pixel circuit is composed of five a‐Si:H TFTs, and it does not require any complicated drive ICs. The OLED current compensation for drive TFT threshold voltage variation has been verified using SPICE simulations.     

An electrostatic discharge model for thin‐film transistor fabrication

Electrostatic discharge (ESD) is a significant cause of yield loss in thin‐film transistor (TFT) array manufacturing. TFT arrays are at increased risk relative to other electronic components because the TFTs are unprotected; the array has a large inherent capacitance, and TFT processing includes many chucking and conveyance steps that result in triboelectric charge generation. To reduce or eliminate ESD‐caused fallout, an understanding must be gained of an ESD event's fundamental physics, including the mechanism of charge generation, ESD event physics, and TFT failure modes. An equivalent circuit model has been developed to address the physics of how ESD events occur. The ESD event scenarios modeled with this circuit are as follows: (1) the substrate glass is lifted from the chuck, resulting in a non‐uniform static charge; (2) this charge induces a voltage on the A‐side components; (3) the substrate is lifted, causing a voltage increases; (4) the uneven charge generated results in voltage gradients between TFTs, resulting in an ESD event. This model combines the effects of TFT substrate lifting and charge generation, with a simplified equivalent circuit representing the TFT array. The behavior of this circuit was simulated with a spice model (Electronics Research Laboratory of the University of California, Berkeley, CA, USA.) to characterize the ESD pulse.     

Modeling of current—voltage characteristics for double‐gate a‐IGZO TFTs and its application to AMLCDs

Abstract— The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double‐gate (DG) a‐IGZO TFTs, when the top‐ and bottom‐gate electrodes are connected together (synchronized), were developed. From these equations, it is found thatsynchronized DG a‐IGZO TFTs can be considered as conventional TFTs with a modified gate capacitance and threshold voltage. The developed models were compared with the top or bottom gate only bias conditions. The validity of the models is discussed by using the extracted TFT parameters for DG coplanar homojunction TFTs. Lastly, the new pixel circuit and layout based on a synchronized DG a‐IGZO TFT is introduced.     

Investigation of the hysteresis phenomenon of an a‐Si:H TFT at an elevated temperature for AMOLED displays

Abstract— The temperature dependence of the hysteresis of an a‐Si:H TFT has been investigated. An a‐Si:H TFT pixel driving scheme has been proposed and investigated. This scheme can eliminate changes in the organic light‐emitting diode (OLED) current caused by hysteresis of an a‐Si:H TFT. The VTH of the a‐Si:H TFT was changed according to the gate‐voltage sweep direction because of the hysteresis of the a‐Si:H TFT. The variation of VTH for a a‐Si:H TFT decreased from 0.41 to 0.17 V at an elevated temperature of 60°C because the sub‐threshold slope (s‐slope) of the a‐Si:H TFT, in the reverse voltage sweep direction, increased more than in the forward voltage sweep direction due to a greater increase in the initial electron trapped charges than the hole charges. Although the OLED current variation caused by hysteresis decreased (～14%) as the temperature increased, the error in the OLED current needed to be improved in order to drive the pixel circuit of AMOLED displays. The proposed pixel circuit can apply the reset voltage (?10 V) before the data voltage for the present frame that was written to fix the sweep direction of the data voltage. The variation in the OLED current caused by hysteresis of the a‐Si:H TFT was eliminated by the fixed voltage sweep direction in the proposed pixel circuit regardless of operating temperature.     

Threshold‐voltage‐compensation methods for AMOLED pixel and analog buffer circuits

Abstract— New pixel‐circuit designs for active‐matrix organic light‐emitting diodes (AMOLEDs) and a new analog buffer circuit for the integrated data‐driver circuit of active‐matrix liquid‐crystal displays (AMLCDs) and AMOLEDs, based on low‐temperature polycrystalline‐silicon thin‐film transistors (LTPS‐TFTs), were proposed and verified by SPICE simulation and measured results. Threshold‐voltage‐compensation pixel circuits consisting of LTPS‐TFTs, an additional control signal line, and a storage capacitor were used to enhance display‐image uniformity. A diode‐connected concept is used to calibrate the threshold‐voltage variation of the driving TFT in an AMOLED pixel circuit. An active load is added and a calibration operation is applied to study the influences on the analog buffer circuit. The proposed circuits are shown to be capable of minimizing the variation from the device characteristics through the simulation and measured results.     

Novel mobile TFT‐LCDs based on SLS technology

Abstract— Single‐crystal‐like silicon (SLS) technology is the most cost‐effective laser‐crystallization process ever invented. The throughput of the SLS process is about two times higher than that of the conventional excimer‐laser annealing (ELA) method. In addition, the performance of the TFTs fabricated by the SLS process is among the best utilized in mass production. Various TFT‐LCDs employing SLS technology, which included a 1.02‐in. full SOG LCD using an icon display for the sub‐display of cellular phones, a 1.9‐in. qVGA TFT‐LCD with a low‐power analog interface employing a low‐voltage driving scheme, and a 3.0‐in. VGA TFT‐LCD compatible with the 480i data format without additional signal processing were developed. Because the SLS process enables us to achieve highly uniform and reliable transistors, it can be effectively utilized in the mass production of mobile TFT‐LCDs with low power consumption and enhanced image quality.     

A novel pixel memory using integrated voltage‐loss‐compensation (VLC) circuit for ultra‐low‐power TFT‐LCDs

Abstract— A novel pixel memory using an integrated voltage‐loss‐compensation (VLC) circuit has been proposed for ultra‐low‐power TFT‐LCDs, which can increase the number of gray‐scale levels for a single subpixel using an analog voltage gray‐scale technique. The new pixel with a VLC circuit is integrated under a small reflective electrode in a high‐transmissive aperture‐ratio (39%) 3.17‐in. HVGA transflective panel by using a standard low‐temperature‐polysilicon process based on 1.5‐μm rules. No additional process steps are required. The VLC circuit in each pixel enables simultaneous refresh with a very small change in voltage, resulting in a two‐orders‐of‐magnitude reduction in circuit power for a 64‐color image display. The advanced transflective TFT‐LCD using the newly proposed pixel can display high‐quality multi‐color images anytime and anywhere, due to its low power consumption and good outdoor readability.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

A new current‐mirror pixel circuit employing poly‐Si TFTs for active‐matrix organic light‐emitting‐diode displays

Abstract— A novel active‐matrix organic light‐emitting‐diode (AMOLED) display employing a new current‐mirror pixel circuit, which requires four‐poly‐Si TFTs and one‐capacitor and no additional signal lines, has been proposed and sucessfully fabricated. The experimental results show that a new current mirror can considerably compensate luminance non‐uniformity and scale down a data current more than a conventional current‐mirror circuit in order to reduce the pixel charging time and increase the minimum data current. Compared with a conventional two‐TFT pixel, the luminance non‐uniformity induced by the grain boundaries of poly‐Si TFTs can be decreased considerably from 41% to 9.1%.     

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.