IXP2400多线程编程设计的研究与实践

由于网络处理器的高性能和可编程灵活性能较好地满足高速数据通信的要求,因此,它在高速网络设备中有着广阔的应用前景.该文介绍了IXP2400的硬件体系结构,阐述了体系结构中针对网络数据处理所作的优化,分析了IXP2400中多线程编程的两种具体实现模式,并在此基础上提出了实际的端口扫描检测应用举例.     

IXP2400网络处理器及其微引擎中多线程实现的研究

网络处理器兼顾了ASIC的高性能和RISC芯片的可编程灵活性,能较好地满足数据通信高速发展的要求,在将来的网络设备中,有广阔的应用前景。IXP2400是Intel公司推出的第二代网络处理器。它采用了高性能的并行体系结构来处理复杂的算法、包内容检测、流量管理和线速转发。多线程技术是IXP2400实现高速数据处理的关键技术。该文介绍了IXP2400的硬件结构及软件开发,并分析了其微引擎中多线程实现的有关技术。     

网络通信处理器在路由器中的应用

网络通信处理器是为提高报文处理效率而出现的专用处理器。该文描述了网络处理器的基本体系结构，并以Motorola通信处理器MPC860为例阐述了路由器的实现方法。     

32位RISC微处理器流水线设计

简要介绍了一个32位嵌入式航空机载RISC微处理器芯片AR S03的体系结构及特色,阐述了处理器的内部各个模块的功能。着重讨论了其流水线的设计思想和设计实现。AR S03处理器的执行部件采用了5级流水结构、较好的冲突控制策略及低功耗的数据通路,实现了简洁、高效、灵活的体系结构。通过Verilog仿真、综合和静态时序分析的结果表明设计达到了预定的设计要求。     

基于IXP1200网络处理器的边缘路由器实现

基于网络处理器的路由器开发是一个热点。文中介绍了基于网络处理器的路由器体系结构，分析了IXP1200网络处理器的硬件体系结构。最后介绍了一种基于IXP1200网络处理器的边缘路由器实现方案。     

基于遗传算法的网络处理器异构资源映射方法研究

随着深亚微米工艺的迅速发展,现代网络处理器芯片广泛采用MPSoC(Multi-Processor System on Chip)体系结构实现,继而需要一种新的设计方法指导网络处理器体系结构设计.本文研究了网络处理器的设计方法,提出了一种基于遗传算法的网络应用到网络处理器异构硬件资源映射方法.该方法首先对网络处理器设计的问题空间进行分析,采用加权数据流进程网络描述网络应用,并参数化各种硬件资源,最后构建遗传算法来完成网络应用到异构硬件资源的映射,形成网络处理器体系结构设计方案.     

基于网络处理器的IPv6路由器设计

分析了当前路由器的体系结构没计。深入研究了网络处理器的技术特点，给出了基于网络处理器的IPv6路由器的设计方案，阐述了此方案在路由查找、报文交换、阻塞管理等方面的问题和解决方法。并讨论了IPv6路由器软件的模块设计。     

分布式转发造就第五代

华为将路由器体系结构的演进历程分为五代,其中第五代 NetEngine 80/40/20路由器的 IP 转发和业务流程处理上采用了可编程的网络处理器(NP)技术.可以实现业务灵活性和高性能硬件转发的结合。路由器体系结构演进在华为看来,第一代路由器的特点是集中转发,固定接口。随着 IP 网络的发展,网络节点增多,第一代路由器的固定网络接口不能满足 IP 网络链路经常变化的要求,第二代路由器把网络接口做成可以插拔的活动模块,用户可以根据需要增加所需要的网络接口模块,不     

网络处理器简介及其微引擎设计

网络规模的膨胀型增长、用户对宽带需求的急速增加、各种新业务的层出不穷和智能化管理、应用可升级的技术需求催生了网络处理器，形成了以网络处理器为核心的新一代网络设备体系结构。该文简要介绍了网络处理器的定义、结构及其特点，分析了网络处理器设计与通用处理器的主要不同点，着重阐述了网络处理器的核心部分——微引擎的结构和设计重点。     

微处理器内安全子系统的安全增强技术

在信息技术快速发展的同时,信息安全变得尤为重要。处理器作为信息系统的核心部件,其安全性对系统安全起到至关重要的决定性作用。在处理器中构建安全可信的执行环境是提升处理器安全性的重要方法,然而很多核心安全技术仍然由片外安全TPM/TCM芯片保证。近年来,作为计算机系统安全基础的安全原点逐渐往处理器中转移。对处理器内安全子系统的安全增强技术展开研究,首先研究安全处理器体系结构;然后对处理器核、互连网络、存储和密码模块等处理器核心模块进行安全增强,同时从系统级角度实现了密钥管理、生命周期、安全启动和抗物理攻击等系统安全防护技术;最后,在一款桌面处理器中实现了一个安全子系统,并进行了分析。     

异构多核处理器体系结构设计研究

多核技术成为当今处理器发展的重要方向,异构多核处理器由于可将不同类型的计算任务分配到不同类型的处理器核上并行处理,从而为不同需求的应用提供更加灵活、高效的处理机制而成为当今研究的热点.本文从体系结构的角度探讨了异构多核处理器设计中的关键点,从内核结构、互连方式、存储系统、操作系统支持、测试与验证、动态电压调节等方面分析...     

基于网络处理器IXP2400系统的软件设计

网络处理器高性能的包处理能力及可编程的灵活性适应了当前网络发展需求，广泛应用于高端路由器、边缘多业务宽带接入、媒体网关和安全等领域。基于网络处理器成功构建一个网络系统的关键在于网络处理器软件系统的设计与开发，其核心问题就是要软件系统充分发挥网络处理器灵活性和高性能的特点，面向网络处理器的硬件体系结构编程，合理利用网络处理器，为优化数据包处理的各种硬件资源设计高效的多处理器、多线程并行机制。本文以网络处理器IXP2400实现高速网络应用为例，介绍基于网络处理器系统的软件开发过程和设计方法，探讨开发高性能的微码软件的策略和技术。首先介绍了基于网络处理器系统的硬件体系结构配置和软件开发框架、应用软件的系统分析和总体设计，着重分析了基于网络处理器系统的多微引擎、多线程的并行处理机制，以及互斥问题和包排序问题的解决方法，最后讨论了系统的性能评估方法。     

Network interfaces for programmable NICs and multicore platforms

The availability of multicore processors and programmable NICs, such as TOEs (TCP/IP Offloading Engines), provides new opportunities for designing efficient network interfaces to cope with the gap between the improvement rates of link bandwidths and microprocessor performance. This gap poses important challenges related with the high computational requirements associated to the traffic volumes and wider functionality that the network interface has to support. This way, taking into account the rate of link bandwidth improvement and the ever changing and increasing application demands, efficient network interface architectures require scalability and flexibility. An opportunity to reach these goals comes from the exploitation of the parallelism in the communication path by distributing the protocol processing work across processors which are available in the computer, i.e. multicore microprocessors and programmable NICs.Thus, after a brief review of the different solutions that have been previously proposed for speeding up network interfaces, this paper analyzes the onloading and offloading alternatives. Both strategies try to release host CPU cycles by taking advantage of the communication workload execution in other processors present in the node. Nevertheless, whereas onloading uses another general-purpose processor, either included in a chip multiprocessor (CMP) or in a symmetric multiprocessor (SMP), offloading takes advantage of processors in programmable network interface cards (NICs). From our experiments, implemented by using a full-system simulator, we provide a fair and more complete comparison between onloading and offloading. Thus, it is shown that the relative improvement on peak throughput offered by offloading and onloading depends on the rate of application workload to communication overhead, the message sizes, and on the characteristics of the system architecture, more specifically the bandwidth of the buses and the way the NIC is connected to the system processor and memory. In our implementations, offloading provides lower latencies than onloading, although the CPU utilization and interrupts are lower for onloading. Taking into account the conclusions of our experimental results, we propose a hybrid network interface that can take advantage of both, programmable NICs and multicore processors.     

Byzantine Agreement in a generalized connected network

Traditionally, the Byzantine Agreement (BA) problem is studied either in a fully connected network or in a broadcast network. A generalized network model for BA is proposed in this paper. A fully-connected network or a broadcast network is a special case of the new network architecture. Under the new generalized network model, the BA problem is reexamined with the assumption of malicious faults on both processors and transmission medium (TM), as opposed to previous studies which consider malicious faults on processors only. The proposed algorithm uses the minimum number of message exchanges, and can tolerate the maximum number of allowable faulty components to make each healthy processor reach a common agreement for the cases of processor failures, TM failures, or processor/TM failures. The results can also be used to solve the interactive consistency problem and the consensus problem     

网络处理器中协处理器设计方法研究及实现

随着深亚微米工艺的迅速发展,现代网络处理器芯片广泛采用MPSoC体系结构实现。针对网络处理器中协处理器的特点,本文研究了其设计方法,提出了三种多个处理单元间的协处理器共享机制,而后在基于NiosⅡ软核的网络处理器中实现了多种协处理器结构,以支持不同的设计需求。     

多核处理器及其对系统结构设计的影响

多核技术成为当今处理器技术发展的重要方向,已经是计算机系统设计者必须直面的现实。从计算机系统结构的角度探讨了同构与异构、通用与多用等多核处理器的类型,分析了典型多核处理器的微结构、工艺等结构特点,讨论了多核处理器对计算机系统结构设计带来的挑战。     

Performance evaluation of network processor architectures: combining simulation with analytical estimation

The designs of most systems-on-a-chip (SoC) architectures rely on simulation as a means for performance estimation. Such designs usually start with a parameterizable template architecture, and the design space exploration is restricted to identifying the suitable parameters for all the architectural components. However, in the case of heterogeneous SoC architectures such as network processors the design space exploration also involves a combinatorial aspect––which architectural components are to be chosen, how should they be interconnected, task mapping decisions––thereby increasing the design space. Moreover, in the case of network processor architectures there is also an associated uncertainty in terms of the application scenario and the traffic it will be required to process. As a result, simulation is no longer a feasible option for evaluating such architectures in any automated or semi-automated design space exploration process due to the high simulation times involved. To address this problem, in this paper we hypothesize that the design space exploration for network processors should be separated into multiple stages, each having a different level of abstraction. Further, it would be appropriate to use analytical evaluation frameworks during the initial stages and resort to simulation techniques only when a relatively small set of potential architectures is identified. None of the known performance evaluation methods for network processors have been positioned from this perspective.We show that there are already suitable analytical models for network processor performance evaluation which may be used to support our hypothesis. To this end, we choose a reference system-level model of a network processor architecture and compare its performance evaluation results derived using a known analytical model [Thiele et al., Design space exploration of network processor architectures, in: Proc. 1st Workshop on Network Processors, Cambridge, MA, February 2002; Thiele et al., A framework for evaluating design tradeoffs in packet processing architectures, in: Proc. 39th Design Automation Conference (DAC), New Orleans, USA, ACM Press, 2002] with the results derived by detailed simulation. Based on this comparison, we propose a scheme for the design space exploration of network processor architectures where both analytical performance evaluation techniques and simulation techniques have unique roles to play.     

A hybrid closed queuing network model for multi-threaded dataflow architecture

In this paper, a closed queuing network model with both single and multiple servers has been proposed to model dataflow in a multi-threaded architecture. Multi-threading is useful in reducing the latency by switching among a set of threads in order to improve the processor utilization. Two sets of processors, synchronization and execution processors exist. Synchronization processors handle load/store operations and execution processors handle arithmetic/logic and control operations. A closed queuing network model is suitable for large number of job arrivals. The normalization constant is derived using a recursive algorithm for the given model. State diagrams are drawn from the hybrid closed queuing network model, and the steady-state balance equations are derived from it. Performance measures such as average response times and average system throughput are derived and plotted against the total number of processors in the closed queuing network model. Other important performance measures like processor utilizations, average queue lengths, average waiting times and relative utilizations are also derived.