新型地锚张弦梁式泥石流格栅坝构件受力的简化计算方法

针对常见泥石流防治结构被冲击破坏的问题，基于“柔性消能”理念，结合张弦梁结构和竖向预应力锚杆技术，提出一种既能改善结构受力性能、增加结构整体抗冲击能力、保证结构安全可靠，又能减小结构构件截面尺寸、节约成本、便于现场施工组装和后期运营维护的新型地锚张弦梁式泥石流格栅坝，并阐述其技术原理。根据泥石流荷载分布和新型地锚张弦梁式泥石流格栅坝的受力特征，给出其简化的内力计算方法；并利用SAP2000建立新结构有限元模型，分析了结构的整体受力，验证了构件简化计算方法的合理性；结合Python语言和Qt De? signer软件开发了相应的设计计算软件，对新型地锚张弦梁式泥石流格栅坝的内力进行求解。结果表明：提出的新结构抗冲击性能好，构件受力均匀；以后设计中应关注竖杆的剪切脆性破坏和立柱偏心受力情况，保证结构安全；变形协调仅使底层张弦梁与竖杆内力偏大，实际工程应用时，应着重验算底层构件，防止其破坏；文中提出的简化计算方法能较准确的反映结构的受力特性，具有一定的合理性，研究可为新型地锚张弦梁式泥石流格栅坝的设计计算和推广应用提供理论依据和技术支持。     

Freeze-drying and mechanical redispersion of aqueous PEDOT:PSS

Poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) films are attracting famous applications in antistatic coating, energy storage and conversion, printed electronics, and biomedical fields due to their conductivity, optical transparency and flexibility. However, PEDOT:PSS has poor dispersion stability during long-term storage and transport. Moreover, the dried PEDOT:PSS films are insoluble in any solvent and cannot be redispersed again. In comparison to bake drying, here, a feasible strategy to achieve mechanically redispersed PEDOT:PSS with the help of freeze-drying process was reported. The redispersed PEDOT:PSS can recover not only the initial characters such as pH, chemical composition, viscosity, and particle size under similar solid contents, but also conductivity and surface morphology of treated films. In addition, the treated film exhibits self-healing properties similar to pristine film in terms of mechanical and electrical properties. This technology enables reuse and overcomes the technical problems of PEDOT:PSS dispersion, realizing real-time processing to meet variable applications.     

大规模多状态计算系统的容错性能分析

针对异构计算节点组成的大规模多状态计算系统的容错性能分析问题，提出了一种计算系统容错性能的评估方法。该方法采用自定义的两级容错性能形式化描述框架进行系统描述，通过构造多值决策图（Multi-value Decision Diagram，MDD）模型对系统进行容错性能建模，并基于构造的模型高效地计算出部件故障的条件下计算系统在特定性能水平上运行的概率，减少了计算的冗余性。实验结果表明，该方法在模型的大小和构建时间上均优于传统方法。该方法的提出将对系统操作员或程序设计者具有重要意义，使其确保系统适合预期应用。     

Coil‐Type Asymmetric Supercapacitor Electrical Cables

Cable‐shaped supercapacitors (SCs) have recently aroused significant attention due to their attractive properties such as small size, lightweight, and bendability. Current cable‐shaped SCs have symmetric device configuration. However, if an asymmetric design is used in cable‐shaped supercapacitors, they would become more attractive due to broader cell operation voltages, which results in higher energy densities. Here, a novel coil‐type asymmetric supercapacitor electrical cable (CASEC) is reported with enhanced cell operation voltage and extraordinary mechanical‐electrochemical stability. The CASECs show excellent charge–discharge profiles, extraordinary rate capability (95.4%), high energy density (0.85 mWh cm⁻³), remarkable flexibility and bendability, and superior bending cycle stability (≈93.0% after 4000 cycles at different bending states). In addition, the CASECs not only exhibit the capability to store energy but also to transmit electricity simultaneously and independently. The integrated electrical conduction and storage capability of CASECS offer many potential applications in solar energy storage and electronic gadgets.     

Adaptive robust boundary control of shaft vibrations under perturbations with unknown upper bounds

This paper presents robust and adaptive boundary control designs to stabilize the two‐dimensional vibration of hybrid shaft model. The hybrid shaft is mathematically represented by a set of partial differential equations, governing the shaft vibrations, coupled to ordinary differential equations, describing rigid body spinning and dynamic boundary conditions. The control objective is to stabilize the transverse vibrations of the perturbed shaft while regulating the spinning rate. To achieve this, the paper first establishes robust boundary control laws that fulfil the control objective in the presence of modeling uncertainties and external disturbances operating over the shaft domain and boundary. Lyapunov‐based analyses show that the proposed robust control exponentially stabilizes the shaft with vanishing distributive perturbations, while assuring ultimately bounded vibrations in the case of nonvanishing perturbations. Then, adaptive control philosophy is utilized to achieve redesigned robust controllers that only use online adaptation of control gains without acquiring the knowledge of bounds on perturbations, as well as dynamic parameters. An advantage of this design is avoiding an overconservative robust control law, which may induce poor stability and chattering in tackling system perturbations with unknown upper bounds. Simulations through finite element method illustrate the results. Copyright © 2014 John Wiley & Sons, Ltd.     

基于改进人工蜂群算法的多目标绿色柔性作业车间调度研究

针对多目标绿色柔性作业车间调度问题（MGFJSP）的特点，提出从碳排放量、噪声和废弃物这3个指标来综合评定环境污染程度，建立了以最小化最大完成时间和环境污染程度为优化目标的MGFJSP模型，并提出了一种改进的人工蜂群算法来求解该模型。算法的具体改进包括：设计了一种三维向量的编码和对应解码方案，在跟随蜂搜索阶段引入一种有效的动态邻域搜索操作来提高算法的局部搜索能力，在侦查蜂阶段提出产生新食物源的策略用于增加种群的多样性。最后进行了实验研究与算法对比，以验证所建模型和所提算法的有效性。     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Small‐Sized High‐Power PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet

This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns.     

SOI光电子集成

SOI（Silicon-on-Insulator)光电子集成已成为十分引人注目的研究课题，其工艺与CMOS工艺完全兼容，可以实现低成本的SOI基整片集成光电子回路。本文综述了近几年来SOI集成光电子器件的发展以及一些最新的研究进展，着重分析几种最新型光无源器件的工作原理和结构，包括SOI光波导、SOI光波导耦合器、SOI光波导开关、相位阵列波导光栅（PAWG）、基于SOI的光探测器等，并介绍了中国科学院半导体所集成光电子国家重点实验室的研究进展。