Scalable and Structured Scheduling

Scheduling a program (i.e. constructing a timetable for the execution of its operations) is one of the most powerful methods for automatic parallelization. A schedule gives a blueprint for constructing a synchronous program, suitable for an ASIC or VLIW processor. However, constructing a schedule entails solving a large linear program. Even if one accepts the (experimental) fact that the Simplex is almost always polynomial, the scheduling time is of the order of a large power of the program size. Hence, the method does not scale well. The present paper proposes two methods for improving the situation. First, a large program can be divided into smaller units (processes), which can be scheduled separately. This is structured scheduling. Second, one can use projection methods for solving linear programs incrementally. This is specially efficient if the dependence graph is sparse.     

Workload Distribution in Fault Simulation

Simulation at the gate level is computationally very expensive.Parallel processing is one technique to reduce simulation time.Possessing knowledge of the distribution of computational activity insimulation can aid in parallelizing it efficiently. We present a newcharacterization of the distribution of the computational workload infault simulation. An empirical analysis shows that the workloaddistribution is circuit specific, and is largely independent of thevector set being simulated. An inexpensive method to predict theworkload distribution is also discussed.     

三维合成炮叠前深度偏移

对国际上标准的SEG/EAEG模型进行了三维合成炮叠前偏移研究。与三维单炮叠前深度偏移不同 ,三维合成炮叠前偏移有一个叠前数据的合成过程 ,由于合成后数据量大大减少 ,所以合成炮偏移的计算量要比单炮偏移小得多。阐述了三维合成炮叠前偏移的实现过程 ,给出了相应公式。对SEG/EAEG盐丘模型的一个数据集进行了MPI并行计算 ,取得了良好的成像效果。所作的较多计算表明了三维合成炮叠前偏移的正确性和有效性 ,这为野外实际数据的三维叠前深度偏移提供了另一条有效途径。     

Map Reduce inspired loop mapping for coarse-grained reconfigurable architecture

Our work investigates how to map loops efficiently onto Coarse-Grained Reconfigurable Architecture （CGRA）. This paper examines the properties of CGRA and builds MapReduce inspired models for the loop parallelization problem. The proposed model has a more detailed performance metric and a more flexible unrolling scheme that can unroll different loop levels with different factors. A Geometric Programming based approach is proposed to resolve the optimization problem of loop parallelization problem. The proposed approach can find the optimal unrolling factor for each level loop, resulting in better parallelization of loops. Experimental results show that the proposed approach achieved up to 44% performance gain compared to the state-of-the-art loop mapping scheme.     

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

In this paper,a TPP(Task-based Parallelization and Pipelining)scheme is proposed to implement AVS(Audio Video coding Standard)video decoding algorithm on REMUS(REconfigurable MUltimedia System),which is a coarse-grained reconfigurable multimedia system.An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning.Several parallel techniques,such as MB(Macro-Block)-based parallel and block-based parallel techniques,and several pipeline techniques,such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation,for performance improvement of the AVS decoder.Also,most computation-intensive tasks in AVS video standards,such as MC(Motion Compensation),IP(Intra Prediction),IDCT(Inverse Discrete Cosine Transform),REC(REConstruct)and DF(Deblocking Filter),are performed in the two RPUs(Reconfigurable Processing Units),which are the major computing engines of REMUS.Owing to the proposed scheme,the decoder introduced here can support AVS JP(Jizhun Profile)1920×1088@39fps streams when exploiting a 200 MHz working frequency.     

异构HPL算法中CPU端高性能BLAS库优化

异构HPL（high-performance Linpack）效率的提高需要充分发挥加速部件和通用CPU计算能力,加速部件集成了更多的计算核心,负责主要的计算,通用CPU负责任务调度的同时也参与计算.在合理划分任务、平衡负载的前提下,优化CPU端计算性能对整体效率的提升尤为重要.针对具体平台体系结构特点对BLAS（basic linear algebra subprograms）函数进行优化往往可以更加充分地利用通用CPU计算能力,提高系统整体效率.BLIS（BLAS-like library instantiation software）算法库是开源的BLAS函数框架,具有易开发、易移植和模块化等优点.基于异构系统平台体系结构以及HPL算法特点,充分利用三级缓存、向量化指令和多线程并行等技术手段优化CPU端调用的各级BLAS函数,应用auto-tuning技术优化矩阵分块参数,从而形成了HygonBLIS算法库.与MKL相比,在异构环境下,HPL算法整体性能提高了11.8%.     

并行化洪水演进模拟研究综述

近年来,并行化洪水演进模拟技术发展迅速,在防汛减灾领域发挥重要作用。在考虑洪水演进模型的数值方法、并行模式和编程技术等因素后,选取一些有代表性的洪水演进模型,分析了同构并行和异构并行洪水演进模型涉及的技术细节,提出并行化模型开发的技术难点和解决方法。最后,提出将来并行化洪水演进模型研发的着力点：非结构网格模型的异构并行化;混合并行的洪水演进模型;适于GPU异构并行的网格形式;并行环境下的实时可视化和交互式计算;基于动态编程语言的模型开发;界面式开发及模型应用推广。     

改进变异算子的差分进化算法并行性分析

针对并行差分进化算法的全局搜索能力和寻优的稳定性弱的现状,基于DE/best/1变异算子提出了一种改进的差分进化算法变异算子.该算子前期采用DE/best/1变异方法,当进化代数超过设定的进化代数值时,采用改进的变异算子.通过拓宽变异算子的搜索域来提高种群的多样性,提高了差分进化算法的寻优能力.对改进变异算子的并行差分进化算法进行了函数测试,实验结果表明:相比普通的变异算子,在相同种群规模的前提下,改进的差分变异算子拓宽了遗传算法的搜索域,提高了算法的全局搜索能力;在不同的种群规模下,改进的变异算子增强了算法的寻优稳定性.     

基于Parallel studio的视频编解码并行化优化

随着计算机技术的不断发展,人们对多媒体技术的实时性有了更高的要求,特别是视频编解码的时间效率.另外,随着多核CPU及相关技术的不断普及,使得原有非并行化程序的性能的不足显现了出来,因此对传统程序的并行化迫在眉睫.本文以目前较流行的视频编解码算法h.263为例,通过一个具体的视频会议系统,分析传统串行编解码算法的性能,通过英特尔Parallel studio并行化分析工具,找到算法的运行瓶颈,然后用英特尔线程构建模块对编解码算法进行并行化优化,取得了良好的效果.     

基于CUDA的并行全搜索运动估计算法

为了提高H.264视频编码效率,基于计算统一设备架构(CUDA)的并行全搜索运动估计算法,并利用GPU强大的计算能力和CUDA优化的存储层次结构,以加速H.264编码中的运动估计.与传统的以牺牲视频质量来提升运动估计性能的方法不同,该算法在保证视频质量的同时,结合运动估计计算密集、计算量大等特点,充分利用CUDA架构的并行性加快运动估计的速度,从而达到提高实时编码速度的目的.在GTX280实验平台上的实验结果显示,采用文中算法比优化的CPU实现可获得高达70倍的加速比.