Design of Deep Convolution Neural Networks for categorical signature classification of raw panchromatic satellite images

Multimedia Tools and Applications - Remote Sensing categorical signature classification has gained significant implications on spatial resolution image analysis due to differences in the...     

Three dimensional reconstruction of brain tumor along with space occupying in lesions

Multimedia Tools and Applications - The three-dimensional models of brain tumors serve as diagnostic assistance for physicians, surgeons, and radiologists. The proposed system establishes an...     

A Survey on Advanced Multiple Access Techniques for 5G and Beyond Wireless Communications

Wireless Personal Communications - This paper summarizes the ongoing research initiatives based on the advanced multiple access techniques towards the fifth generation (5G) wireless communication...     

A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis

Wireless Personal Communications - Today’s high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or...     

An Octagonal Shaped Monopole Antenna for UWB Applications with Band Notch Characteristics

Wireless Personal Communications - This article presents a microstrip-fed octagonal shaped monopole antenna with dual band notched characteristics for UWB applications. Partial ground plane has...     

A bi-layer optimization approach for a hybrid flow shop scheduling problem involving controllable processing times in the steelmaking industry

A steelmaking-continuous casting (SCC) scheduling problem is an example of complex hybrid flow shop scheduling problem (HFSSP) with a strong industrial background. This paper investigates the SCC scheduling problem that involves controllable processing times (CPT) with multiple objectives concerning the total waiting time, earliness/tardiness and adjusting cost. The SCC scheduling problem with CPT is seldom discussed in the existing literature. This study is motivated by the practical situation of a large integrated steel company in which the just-in-time (JIT) and cost-cutting production strategy have become a significant concern. To address this complex HFSSP, the scheduling problem is decomposed into two subproblems: a parallel machine scheduling problem (PMSP) in the last stage and an HFSSP in the upstream stages. First, a hybrid differential evolution (HDE) algorithm combined with a variable neighborhood decomposition search (VNDS) is proposed for the former subproblem. Second, an iterative backward list scheduling (IBLS) algorithm is presented to solve the latter subproblem. The effectiveness of this bi-layer optimization approach is verified by computational experiments on well-designed and real-world scheduling instances. This study provides a new perspective on modeling and solving practical SCC scheduling problems.     

Modeling the effect of deep traps on the capacitance–voltage characteristics of p-type Si-doped GaAs Schottky diodes grown on high index GaAs substrates

Numerical simulation, using SILVACO-TCAD, is carried out to explain experimentally observed effects of different types of deep levels on the capacitance–voltage characteristics of p-type Si-doped GaAs Schottky diodes grown on high index GaAs substrates. Two diodes were grown on (311)A and (211)A oriented GaAs substrates using Molecular Beam Epitaxy (MBE). Although, deep levels were observed in both structures, the measured capacitance–voltage characteristics show a negative differential capacitance (NDC) for the (311)A diodes, while the (211)A devices display a usual behaviour. The NDC is related to the nature and spatial distribution of the deep levels, which are characterized by the Deep Level Transient Spectroscopy (DLTS) technique. In the (311)A structure only majority deep levels (hole traps) were observed while both majority and minority deep levels were present in the (211)A diodes. The simulation, which calculates the capacitance–voltage characteristics in the absence and presence of different types of deep levels, agrees well with the experimentally observed behaviour.     

Conventional and machine learning approaches as countermeasures against hardware trojan attacks

Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits (ICs) in non-trustworthy outsourcing foundries to reduce the cost, thus, leaving space for a synchronous form of virus, known as Hardware Trojan (HT), to be developed. HTs leak encrypted information, degrade device performance or lead to total destruction. To reduce the risks associated with these viruses, various approaches have been developed aiming to prevent and detect them, based on conventional or machine learning methods. Ideally, any undesired modification made to an IC should be detectable by pre-silicon verification/simulation and post-silicon testing. The infected circuit can be inserted in different stages of the manufacturing process, rendering the detection of HTs a complicated procedure. In this paper, we present a comprehensive review of research dedicated to countermeasures against HTs embedded into ICs. The literature is grouped in four main categories; (a) conventional HT detection approaches, (b) machine learning for HT countermeasures, (c) design for security and (d) runtime monitor.