Integrated circuit and system design for renewable energy inverters

This study proposes that a novel integrated circuit (IC) and system design for renewable energy inverters can harvest renewable energy to power direct current (DC) and alternating current (AC) loads. In addition, an intelligent synthesis and management tool is developed to design the proposed system and to judge the system’s operational maintenance decisions. Finally, a renewable energy inverter’s information is posted to an online system. Users can obtain the proposed system’s information at any time and place. The accurate and superior performance of the proposed IC and system is confirmed by computer simulations and experimental results.     

Remarkably enhanced energy storage properties of lead-free Ba0.53Sr0.47TiO3 thin films capacitors by optimizing bottom electrode thickness

The lead-free Ba_0.53Sr_0.47TiO₃ (BST) thin films buffered with La_0.67Sr_0.33MnO₃ (LSMO) bottom electrode of different thicknesses were fabricated by pulsed laser deposition method on a (001) SrTiO₃ substrate. It was found that the roughness of electrode decreases and substrate stress relaxes gradually with the increase of LSMO thickness, which is beneficial for weakening local high electric field and achieving higher E_b. Therefore, the recoverable energy density (W_rec) of BST films can be greatly improved up to 67.3 %, that is, from 30.6 J/cm³ for the LSMO thickness of 30 nm up to 51.2 J/cm³ for the LSMO thickness of 140 nm after optimizing the LSMO thickness. Furthermore, the thin film capacitor with a 140 nm LSMO bottom electrode shows an outstanding thermal stability from 20 °C to 160 °C and superior fatigue resistance after 10⁸ electrical cycles with only a slightly decrease of W_rec below 1.6 % and 3.7 %, respectively. Our work demonstrates that optimizing bottom electrodes thickness is a promising way for enhancing energy storage properties of thin-film capacitors.     

Study of metal assisted anisotropic chemical etching of silicon for high aspect ratio in crystalline silicon solar cells

Textured surface is commonly used to enhance the efficiency of silicon solar cells by reducing the overall reflectance and improving the light scattering. In this study, a comparison between isotropic and anisotropic etching methods was investigated. The deep funnel shaped structures with high aspect ratio are proposed for better light trapping with low reflectance in crystalline silicon solar cells. The anisotropic metal assisted chemical etching (MACE) was used to form the funnel shaped structures with various aspect ratios. The funnel shaped structures showed an average reflectance of 14.75% while it was 15.77% for the pillar shaped structures. The average reflectance was further reduced to 9.49% using deep funnel shaped structures with an aspect ratio of 1:1.18. The deep funnel shaped structures with high aspect ratios can be employed for high performance of crystalline silicon solar cells.     

Formation of ST12 phase Ge nanoparticles in ZnO thin films

In this work, we focus on the Ge nanoparticles (Ge-np) embedded ZnO multilayered thin films. Effects of reactive and nonreactive growth of ZnO layers on the rapid thermal annealing (RTA) induced formation of Ge-np have been specifically investigated. The samples were deposited by sequential r.f. and d.c. sputtering of ZnO and Ge thin film layers, respectively on Si substrates. As-prepared thin film samples have been exposed to an ex-situ RTA at 600 °C for 60 s under forming gas atmosphere. Structural characterizations have been performed by X-ray Diffraction (XRD), Raman scattering, Secondary Ion Mass Spectroscopy (SIMS), and Scanning Electron Microscopy (SEM) techniques. It has been realized that reactive or nonreactive growth of ZnO layers significantly influences the morphology of the ZnO: Ge samples, most prominently the crystal structure of Ge-np. XRD and Raman analysis have revealed that while reactive growth results in a mixture of diamond cubic (DC) and simple tetragonal (ST12) Ge-np, nonreactive growth leads to the formation of only DC Ge-np upon RTA process. Formation of ST12 Ge-np has been discussed based on structural differences due to reactive and nonreactive growth of ZnO embedding layer.     

GaN and AlGaN high-voltage rectifiers grown by metal-organic chemical-vapor deposition

In this paper, we report the study of the electrical characteristics of GaN and AlGaN vertical p-i-n junctions and Schottky rectifiers grown on both sapphire and SiC substrates by metal-organic chemical-vapor deposition. For GaN p-i-n rectifiers grown on SiC with a relatively thin “i” region of 2 μm, a breakdown voltage over 400 V, and forward voltage as low as 4.5 V at 100 A/cm² are exhibited for a 60-μm-diameter device. A GaN Schottky diode with a 2-μm-thick undoped layer exhibits a blocking voltage in excess of ∼230 V at a reverse-leakage current density below 1 mA/cm², and a forward-voltage drop of 3.5 V at a current density of 100 A/cm². It has been found that with the same device structure and process approach, the leakage current of a device grown on a SiC substrate is much lower than a device grown on a sapphire substrate. The use of Mg ion implantation for p-guard rings as planar-edge terminations in mesageometry GaN Schottky rectifiers has also been studied.     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.     

The growth and characterization of AlGaAs double heterostructures for the evaluation of reactor and source quality

AlGaAs double heterostructures are grown by low-pressure metalorganic chemical vapor deposition to evaluate the level of oxygen contamination in different trimethylaluminum sources. Effects of arsine purifiers, misoriented substrates, atmospheric exposure of the growth chamber, and possible phosphorus contamination are also studied. Extensive characterization is performed on these films by a variety of methods, including high-resolution x-ray diffraction, photoluminescence (PL), time-resolved photoluminescence, and secondary-ion mass spectrometry. The PL intensities for structures grown with the low-alkoxide grade are reproducibly much greater than those grown with the regular-grade TMA1. The use of AsH₃ purification improves the PL intensity.     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

基于片上DC-DC的CMOS光接收机前置放大器

利用CSMC 0.6μm CMOS工艺,设计了基于片上DC-DC转换器的光接收机前置放大器。电路采用可调跨阻放大器与片上DC-DC结构,有效地克服了单端跨阻放大器易受电源波动的干扰,并解决了高灵敏度与低失真相互矛盾的问题。模拟结果表明,输入动态范围为83 dB(峰-峰值=0.2μA~3 mA),等效输入电流噪声为1.2 pA/Hz(155 MHz),可稳定工作在155 Mb/s速率上;在5 V电源电压下,功耗为95 mW。