一个面向语义的解释器自动生成技术

本文给出从指称语义自动生成解释器后端的一种技术.解释器被表示成PASCAL_like形式.     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

用一个初始状态生成伪穷尽测试集

本文给出了一种适合于级敏扫描方法（ＬＳＳＤ）的伪穷尽测试集生成方法。通过测试码生成电路中增加状态跳变控制电路，使得只需要一个初始状态就可生成整个伪穷尽测试集。由于这个特点，消除了必须在ＲＯＭ中存储多个初始状态的要求，从而简化了测试控制电路及测试过程。     

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.     

通用菜单系统—UMS

下拉菜单作为应用软件系统的用户界面已成为一种趋势。本文提供一种可以在UNIX和DOS操作系统环境下运行的通用菜单系统UMS（Universal Menu System)。文中对UMS中菜单的数据结构、菜单的用户描述、菜单系统程序的自动生成、菜单的初始化、菜单的实现技术和操作以及应用软件的耦合等技术问题都进行了详细的讨论。同时也指出了软件存在的问题。     

一种派生式与创成式相结合的CAPP系统

本文结合为某机械厂开发的实用计算机辅助工艺设计系统(JJCAPP),论述了一种兼有派生式和创成式特点的综合式工艺自动设计方法.     

FDDI及其网络规划设计

从参考模型等方面阐述了FDDI标准，讨论了FDDI的主要组网方式，并以实例阐述了网络的规划设计。     

Synthesizing Energy-Efficient Embedded Systems with LOPOCOS

In this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimization steps during design space exploration for DVS enable architectures. The optimization steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimization for scheduling and communication mapping based on genetic algorithm, optimizes simultaneously execution order and communication mapping towards the utilization of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimizationsteps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm.     

通讯网的演进

在光纤高速传输技术、光交换与智能光网等与宽带接入、多媒体、3G等网络应用技术的推动下，建设基于IPv6协议的IP基础电信网成为可能。现在IP网正在朝着有序的、可管理的、有QoS保障的、可以支持各类业务的综合业务基础网演进。电信网也正在从网络接入层上、从长途网络层面上、从本地网络层面上、从固定网向含3G在内的移动网络等方面向支持IP技术及其综合业务的方面全面推进。     

Determination of generation lifetime fromC-t transients under linear voltage ramp bias

When a linear voltage ramp is applied to the gate of a MOS capacitor, a capacitancetime (C-t) transient is observed. The MOS capacitor is biased into strong inversion before applying the voltage ramp in order to eliminate surface generation. FromC-t transient curve obtained experimentally the minority carrier generation lifetime in semiconductor can be determined. The experimental results show that for the same sample the lifetimes extracted fromC-t curves under varying voltage sweep rates are close each other, and they are consistent with the lifetimes extracted by saturation capacitance method.