Design and Characterization of a New pVII Combinatorial Phage Display Peptide Library for Protease Substrate Mining Using Factor VII Activating Protease (FSAP) as Model

We describe a novel, easy and efficient combinatorial phage display peptide substrate-mining method to map the substrate specificity of proteases. The peptide library is displayed on the pVII capsid of the M13 bacteriophage, which renders pIII necessary for infectivity and efficient retrieval, in an unmodified state. As capture module, the 3XFLAG was chosen due to its very high binding efficiency to anti-FLAG mAbs and its independency of any post-translational modification. This library was tested with Factor-VII activating protease (WT-FSAP) and its single-nucleotide polymorphism variant Marburg-I (MI)-FSAP. The WT-FSAP results confirmed the previously reported Arg/Lys centered FSAP cleavage site consensus as dominant, as well as reinforcing MI-FSAP as a loss-of-function mutant. Surprisingly, rare substrate clones devoid of basic amino acids were also identified. Indeed one of these peptides was cleaved as free peptide, thus suggesting a broader range of WT-FSAP substrates than previously anticipated.     

并联有源滤波器的改进重复控制策略研究

针对三相整流负载产生的6k±1次谐波,提出静止坐标系下的改进型6k±1重复控制策略。同时将比例控制与改进型重复控制相结合,设计改进重复控制并联比例的复合控制结构。为减小改进重复控制中延时环节不为整数的影响,采用基于Lagrange插值近似的FIR滤波器逼近分数延时特性。最后对系统进行稳定性分析和详细设计方法进行推导。通过Matlab仿真验证改进重复控制策略能有效跟踪6k±1次谐波且具有良好的补偿效果,动态响应较快。     

ZnO基薄膜晶体管的研究

ZnO是一种宽带隙的光电半导体材料,能应用于很多领域,如可用在压敏变阻器、声表面波器件、气敏元件、紫外光探测等。ZnO也可以作为有源层应用于薄膜晶体管(TFT)中。ZnO基薄膜晶体管具有以下突出优势:对于可见光部分平均具有80%以上的透射率,迁移率可以高达36cm2/V·s,开/关电流比大于106,可在较低温度(甚至室温)下制备。基于这些优点,ZnOTFT具有取代有源矩阵液晶显示器中常规a-SiTFT的趋势。同时对ZnOTFT的研究也推动了透明电子学的发展。本文阐述了ZnOTFT优越的电学性能,指出了其目前尚存在的不足,并对其发展前景进行了展望。     

图形点阵式液晶显示器MSP-G320240在高速处理器DSP中的应用

介绍了内置SD1335控制器的图形液晶显示器MSP-G320240的工作原理及应用方法，给出了MSP-G320240液晶显示器同DSP的简单接口电路，同时给出了相应的液晶显示器的初始化和清显示区的具体程序。     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

基于对比折射法的三维静校正技术及其应用

在地形起伏剧烈、速度和厚度横向变化大的地区，折射静校正技术的应用受到诸多限制，主要表现在不能准确地识别和拾取来自于地下连续地质界面的折射波，使得精确求取的长波长静校正量困难。为此，提出了一种基于对比折射法的三维静校正技术。介绍了这种静校正技术的方法原理和特点，基于对比折射法的折射波至拾取实质上是一个折射层的对比分析解释过程，因此能准确地拾取折射波至，精确地求解低速带的绝对延迟时；然后利用延迟时和近地表速度模型（等效，时深，空变）反演表层模型，最终一次性完成基准面静校正（包含低速带校正和高程校正）。在黄土塬、沙漠以及沙漠和山地的接合部等地区，利用基于对比折射法的三维静校正技术进行静校正处理，使资料的品质得到了明显改善，反射同相轴连续性好，信噪比和分辨率高，构造形态清晰可靠，提高了勘探精度。     

基于光纤环的光缓存器

提出了一种基于光纤环的光缓存器的结构,对结合半导体光放大器作光开关的此结构的物理模型进行了详细描述,并根据此模型分析了其增益、噪声、信噪比等方面的特性.     

地震数据采集系统延迟时间研究与分析

文章分析了影响地震采集系统延迟时间的因素,并根据系统延迟的理论对产生的原因进行了论证.同时对实际生产中的测试方法进行了阐述研究和分析,提出了新的测试方法,并结合实际生产提出了合理性建议.     

Performance characteristics of cascaded delay‐line node architectures in single‐path interconnection networks

Internally buffered multistage interconnection network architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded fibre delay line architectures can be seen as possible realizations of output and shared buffering in a 2 × 2‐switching element. These approaches can be used as buffered node architecture in a Banyan like interconnect. In this paper, we investigate and compare these approaches by using simulation methods. Different performance metrics, such as normalized throughput, average packet delay, packet loss rate and buffer utilization have been used under uniform and non‐uniform traffic models. Results show that the TC‐chain node Banyan network offer an improved normalized throughput and average packet delay performances under both traffic models without disrupting first‐in‐first‐out order of arrivals. The switched delay‐line requires fewer switching elements than TC and TTC architectures but at the cost of high packet delay. Copyright © 2004 John Wiley & Sons, Ltd.     

CMOS缓冲器的时延估算模型

随着集成电路生产工艺的进展，互连线在集成电路设计中的影响越来越大。为了减小互连线的影响，通常在芯片互连中插入缓冲器，但这样做会增加时延。因此，为了精确地对系统进行时延估计，必须对缓冲器的时延进行估算。基于Sakurai的器件模型，提出了一种新的缓冲器时延估算模型。