抗交串自适应噪声对消系统的算法实现

针对一般的自适应噪声对消系统性能上存在的不足,引入了抗交串自适应噪声对消系统.抗交串自适应噪声对消系统在形式上由两个典型的自适应噪声对消模块串接而成.抗交串自适应噪声对消系统无须预先知道信号和噪声的特征,却能够相当好地抑制噪声的影响,又使有用信号不产生畸变.该文叙述了该系统的算法实现.计算机仿真结果表明,在强噪声环境背景下,该算法将功率信噪比提高了50db左右,而且运算速度快.该算法对某些特定采样信号的分析和处理有重要意义.     

光伏焦平面器件串音效应的检测图形测试法

根据长波红外焦平面器件研制的需要，在对器件串光效应和测试原理进行分析的基础上，本文首次提出用检测图形测试的方法测量红外焦平面阵列中探测器之间的串音效应。对用于检测光伏焦平面阵列光串音效应的检测图形的结构和原理，具体的测试设备和测试方法，以及由结构设计差异和检测管响应率差异可能引入的误差进行了讨论，并根据红外长波焦平面器件研制过程中的实际测试经验，给出了实用的误差消除方法。在长波ＨｇＣｄＴｅ焦平面阵列的实际研制过程中，该方法对工艺机理的分析和器件参数测试都起了重要的作用。此测试法所用测试设备与常规光电器件测试设备相同，避免了在串音测试上依赖于目前尚不成熟的红外长波小光点技术。     

A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips

This paper proposes a power-efficient flow-control method to tackle the problem of crosstalk faults in Network-on-Chips (NoCs). The method, called FRR (Flit Reordering/Rotation), combines three coding mechanisms to entirely eliminate opposite direction transitions (OD transitions) as the source of crosstalk faults in NoC communication channels. The first mechanism, called flit-reordering, reorders flits of every packet to find a flit sequence which produces the lowest number of OD transitions on NoC channels. The second mechanism called flit-rotation, logically rotates the content of every flit of the packet with respect to previously sent flit to achieve even more reduction in the number of OD transitions. Finally, the third mechanism called flit-insertion, investigates flits of the packet to find the OD transitions which are not removed by first and second mechanisms. This mechanism inserts null-flits between the required flits to completely eliminate appearance of OD transitions on NoC channels. Evaluation of FRR method is done in two ways: (1) VHDL-based simulations are carried out for 16- and 32-bit channels when maximum reorderings and maximum rotations in the first and second mechanisms are limited to 2, 4, and 8. (2) An analytical model is developed to calculate and compare the expected number of OD transitions in an unprotected NoC as well as an FRR-enabled NoC. Both simulation and analytical results confirm that the FRR method completely removes crosstalk faults from NoC channels. In addition, VHDL simulations show that the FRR method provides a remarkable power saving, since the method reduces the number of transitions in NoC channels by at least 32.8%.     

Analysis and simulation of a novel gradually low-K dielectric structure for crosstalk reduction in VLSI

Crosstalk noise and delay uncertainty are two major problems in modern very large scale integration (VLSI) design. To overcome these difficulties, a new dielectric structure is proposed for integrated circuits, which is in contrast to the conventional Cu/low-K technology. Both structures are simulated employing a field solver and a time domain simulator. Using the new dielectric structure, near- and far-end crosstalk noises are reduced 45.2% and 15% in the test dimensions, respectively. The proposed structure, called gradually low-K, exhibits negligible side-effects in terms of delay and power consumption. Therefore, it is shown that the gradually low-K structure is a relevant choice to overcome the crosstalk and delay uncertainty problems, especially in the global interconnects tier.     

An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip

With advance in technology and working frequency reaching gigahertz, designing and testing interconnects have become an important issue. In this paper, we proposed a BIST-based boundary scan architecture to at-speed test of crosstalk faults for inter-switch communication links in network on chip. This architecture includes enhanced cells intended for MVT model test patterns generation and analysis test responses. One new instruction is used to control cells and TPG controller in the at-speed test mode in order to fully comply with conventional IEEE 1149.1 standard.     

Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

This paper illustrates the crosstalk phenomenon and its impact on the design of mixed analog/digital circuits with high accuracy specifications. Generation of digital disturbs, propagation through the substrate, and effects on analog devices are considered, with particular emphasis on integrated circuits realized on heavily doped substrate, where traditional shielding is less effective. Techniques to reduce analog/digital crosstalk are reviewed and discussed. A simple modeling approach is presented, suitable for the analysis of crosstalk effects using a conventional electrical simulator (SPICE). Experimental results on a test chip are presented to validate the modeling approach.     

复用技术耦合率失真优化控制的多图像并行加密机制研究

为了解决当前多图像加密机制存在串扰效应以及失真现象等难题,本文并提出了复用技术耦合率失真控制优化的多图像并行加密机制。基于DCT（Discrete Cosine Transform）变换与Zigzag扫描,设计复用技术,将多个明文压缩成一个复合置乱图像;并引入结构相似度,设计率失真控制优化技术,嵌入到复用技术中,优化失真值,减少失真度;再利用2D Arnlod混沌映射对复合置乱图像进行二次置乱;再结合混沌相位掩码,构造双重加密函数,对置乱图像进行扩散。仿真实验结果表明：本文加密机制高度安全,具备优异的加密质量与强烈的密钥敏感性能;且与当前多图像加密机制相比,本文算法的解密质量更加优异,更能降低串扰效应。     

High performance SOI CMOS pixel sensor with surrounding N+ trench electrode

In this paper, an advanced SOI CMOS pixel (ASCP) detector structure with deep N+ trench electrode is researched and simulated. For this pixel structure, the N+ trench cathode surrounds the P+ trench anode, and they are both connected from the topside. The cathode is in the function of charge share shielding, it isolates the neighbor pixels, and avoids the crosstalk happening of electron hole pairs. Furthermore, the parallel trench electrodes between anode and cathode have reduced the fully depleted voltage, and the bias voltage can be controlled from the core I/O interface. In addition, the ASCP has the better radiation resistance capacity as compared with the Conventional SOI CMOS pixel detector and the Three-Dimension (3D) CMOS detector, due to the low fully depleted voltage and short carrier drift distance. Numerical simulation results show that the ASCP detector has the better charge collecting capacity in low driving voltage, and it is more suitable to detect the back-illumination X-ray ⁵⁵Fe.     

Dynamic noise model and its application to high speed circuit design

A dynamic noise model is developed and applied to analyze the noise immunities of precharge-evaluate circuits. With cross-talk being the main source of noise injection in the circuit, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified through HSPICE simulation on DOMINO gates. Based on this dynamic noise model, a tool is developed and applied to find the static and dynamic noise-margins at various points in the circuit with the effects of charge share and power/ground bounce taken into account. Obtained noise-margins are translated into maximum allowable coupling capacitances between the nodes for different types of precharge-evaluate logic circuits. The results show the difference in dynamic noise immunities in different logic families. Accurate estimates of dynamic noise-margins and coupling capacitance bounds will help design robust CMOS circuits.     

Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

With the scaling development of the minimum lithographic size, the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule. When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD imagepixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction, which results in pixel crosstalk. The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling. Some suppressed crosstalk methods have been reviewed. The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.