基于过零检测的流水线型ADC的设计

该文对比传统基于运放结构的MDAC,介绍了基于过零检测电路ZCBC(zero-crossingbased circuit)的MDAC结构。该结构可以实现轨到轨的信号范围,更加适用于深亚微米下流水线型ADC的设计。并采用0.18μm CMOS工艺,设计了一款10bit 10MSPS 1.5bit/级的流水线型ADC。仿真结果表明:在采样频率为10MHz,输入信号频率为1MHz时,SFDR为66.39dB,ENOB为8.57bits,THD为-62.30dB,DNL为1.36LSB,INL为2.24LSB。     

用于流水线模数转换冗余校正的溢出判断技术

基于流水线A/D转换器冗余位数字校正(RSD)理论,针对其无法判断信号溢出的不足,提出了一种用于冗余校正的溢出判断(OR)技术。该技术通过调整第一级子A/D转换器和编码电路及OR逻辑电路和选择开关电路来实现。仿真结果表明,采用该技术产生的OR=c1 co c2逻辑能显示输入是否发生溢出,并控制多路开关选择正确的数字输出。     

Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs

Dither-based digital background calibration algorithm has been used to eliminate the influence of linear and nonlinear errors in pipelined ADC. However, this algorithm suffers from two disadvantages: too slow convergent speed and deduction of transmitting signal’s amplitude in analog circuits due to dither injection. Input-dependent variable-amplitude dither-based algorithm is used in this paper to conquer both disadvantages. This proposed algorithm is implemented in a 14-bit, 100 MHz sample-rate pipelined ADC. The simulation results illustrate signal-to-noise and distortion (SINAD) of 76.56 dB after calibration of linear and nonlinear errors. Furthermore, the convergent speed is improved much more.     

Platform-based mixed signal design: Optimizing a high-performance pipelined ADC

We apply Platform-Based Design (PBD) to the power optimization of a 14 bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) in a mixed signal formulation. A platform is a library of components and interconnects, each characterized with a set of behavioral, performance and composition models, that is used to raise the level of abstraction to enable system-level design. PBD is a meet-in-the-middle methodology that consists of two phases. The bottom-up phase generates a set of platform libraries that are exploited in the system hierarchy. The top-down phase allows exploring feasible solutions within the platform libraries and selecting the optimum implementation. To evaluate the cost of each implementation, the behavioral models available through platform abstraction are used both for digital and analog components. We provide an example of the use of the methodology and its features for analog circuits by modeling two amplifiers with different topologies as analog components, showing details of the analog characterization process. Then, we create a mixed signal platform library as a combination of an analog and a digital platform (bottom-up phase). The top-down phase performs optimization across the analog/digital boundary to minimize power consumption constrained to given noise and linearity requirements. Simulation results show that interesting power saving can be achieved, as much as 64% compared with an original hand-optimized ADC. Pierluigi Nuzzo received the Laurea degree in electrical engineering from the University of Pisa, Italy, in 2003, and the Diploma from the Scuola Superiore Sant’Anna, Pisa, in 2004, both with honors. Since 2004, he has been with the Department of Information Engineering, University of Pisa, where he is currently working toward the Ph.D. degree in electrical engineering and computer science. During summer 2002 he was with the Fermi National Accelerator Laboratory, Batavia, IL as a student intern working on ASIC testing. From August 2004 to February 2005 he was with IMEC, Leuven, Belgium, as a visiting scholar, working on low power A/D converter design for ultra-wide band applications. His research interests include high speed, low power analog and mixed-signal circuits in CMOS technology, digital calibration of ADCs, system level mixed-signal design and design methodologies. Mr. Nuzzo received first place in the operational category and best overall submission in the 2006 DAC/ISSCC student design competition. Fernando De Bernardinis received the Laurea degree in Electrical Engineering from the University of Pisa, Italy, in 1996 and the M.S. degree and Ph.D. degree from the University of California at Berkeley in 2001 and 2005, respectively. Between 1992 and 1996 he was at the Scuola Superiore S. Anna in Pisa. From 1997 to 1998 he collaborated with the PARADES research center in Rome. During the summers 1999 and 2000 he was at the ST Berkeley labs, working on wireless embedded system design. From 2000 to 2006 he was assistant professor at the Department of Information Engineering at the University of Pisa, Italy. His research interests include mixed-signal design, analog CAD, system level analog design and design methodologies. In 2006 he has joined Marvell Semiconductors, Pavia, Italy, where he works on mixed-signal and RF system design. Alberto Sangiovanni Vincentelli holds the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California at Berkeley. He has been on the Faculty since 1976. He obtained an electrical engineering and computer science degree (“Dottore in Ingegneria”) summa cum laude from the Politecnico di Milano, Milano, Italy in 1971. In 1980–1981, he spent a year as a Visiting Scientist at the Mathematical Sciences Department of the IBM T.J. Watson Research Center. In 1987, he was Visiting Professor at MIT. He has held a number of visiting professor positions at Italian Universities, including Politecnico di Torino, Universita’ di Roma La Sapienza, Universita’ di Roma Tor Vergata, Universita’ di Pavia, Universita’ di Pisa, Scuola Sant’Anna. He was a co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. He is the Chief Technology Adviser of Cadence. He is a member of the Board of Directors of Cadence and the Chair of the Technology Committee, UPEK, a company he helped spinning off from ST Microelectronics, where he is the Chair of its Nominating and Governance Committee and a member of the Audit Committee, Sonics, where he serves as the Chair of the Nominating and Governance Committee, Gradient, where he is a member of the Compensation committee, Accent, an ST Microelectronics-Cadence joint venture he helped founding, and Value Partners. He is the Technology Advisor to the President of the Abruzzo Region. He is a member of the HP Strategic Technology Advisory Board, of the Science and Technology Advisory Board of General Motors and of the Scientific Council of the Tronchetti Provera foundation. He consulted for many companies including Bell Labs, IBM, Intel, United Technology, COMAU, Magneti Marelli, Pirelli, BMW, Daimler-Chrysler, Fujitsu, Kawasaki Steel, Sony, ST and Hitachi. He was an advisor to the Singapore Government for microelectronics and new ventures. He has consulted as Technology Partner for Greylock Ventures and for Vertex Investment. He served as witness in US Congressional investigations on competitiveness of the US economy. He is the founder and Scientific Director of the Project on Advanced Research on Architectures and Design of Electronic Systems (PARADES), a European Group of Economic Interest supported by Cadence, Magneti-Marelli and ST Microelectronics. He is a member of the Advisory Board of the Lester Center for Innovation of the Haas School of Business and of the Center for Western European Studies and a member of the Berkeley Roundtable of the International Economy (BRIE). He is a member of the High-Level Group and of the Steering Committee of the EU Artemis Technology Platform. In 1981, he received the Distinguished Teaching Award of the University of California. He received the worldwide 1995 Graduate Teaching Award of the IEEE (a Technical Field award for “inspirational teaching of graduate students”). In 2002, he was the recipient of the Aristotle Award of the Semiconductor Research Corporation. He has received numerous research awards including the Guillemin-Cauer Award (1982–1983), the Darlington Award (1987–1988) of the IEEE for the best paper bridging theory and applications, and two awards for the best paper published in the Transactions on CAS and CAD, three best paper awards and one best presentation awards at the Design Automation Conference. In 2001, he was given the prestigious Kaufman Award of the Electronic Design Automation Council for pioneering contributions to EDA. He is an author of over 700 papers and 15 books in the area of design tools and methodologies, large-scale systems, embedded controllers, hybrid systems and innovation. Dr. Sangiovanni-Vincentelli has been a Fellow of the IEEE since 1982 and a Member of the National Academy of Engineering, the highest honor bestowed upon a US engineer, since 1998.     

Performance analysis of a QoS capable cluster interconnect

The growing use of clusters in diverse applications, many of which have real-time constraints, requires quality-of-service (QoS) support from the underlying cluster interconnect. All prior studies on QoS-aware cluster routers/networks have used simulation for performance evaluation. In this paper, we present an analytical model for a wormhole-switched router with QoS provisioning. In particular, the model captures message blocking due to wormhole switching in a pipelined router, and bandwidth sharing due to a rate-based scheduling mechanism, called VirtualClock. Then we extend the model to a hypercube-style cluster network. Average message latency for different traffic classes and deadline missing probability for real-time applications are computed using the model.

We evaluate a 16-port router and hypercubes of different dimensions with a mixed workload of real-time and best-effort (BE) traffic. Comparison with the simulation results shows that the single router and the network models are quite accurate in providing the performance estimates, and thus can be used as efficient design tools.     

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing

In order to guarantee both performance and programmability demands in 3D graphics applications, vector and multithreaded SIMD architectures have been employed in recent graphics processing units. This paper introduces a novel instruction-systolic array architecture, which transfers an instruction stream in a pipelined fashion to efficiently share the expensive functional resources of a graphics processor. Specifically, cache misses and dynamic branches can cause additional latencies and complicated management in these parallel architectures. To address this problem, we combine a systolic execution scheme with on-demand warp activation that handles cache miss latency and branch divergence efficiently without significantly increasing hardware resources, either in terms of logic or register space. Simulation indicates that the proposed architecture offers 25% better performance than a traditional SIMD architecture with the same resources, and requires significantly fewer resources to match the performance of a typical modern vector multi-threaded GPU architecture.     

补偿流水线A/D转换器级间增益误差的后台校正技术

在分析流水线A/D转换器中残差放大器电容匹配性和运放的有限增益引起的误差对信号传输影响的基础上,基于冗余位校正流水线A/D转换器结构,通过在信号通路中加入由伪随机码控制的校正信号测量上述误差的方法,在后台校正输出数字信号中的级间增益误差。通过Mat-lab对A/D转换器进行了系统级仿真。结果表明,12位A/D转换器系统的SFDR提高了31.8dB,SNDR提高了11.5 dB,INL减小了3.43 LSB,DNL减小了0.21 LSB。     

ADC中基于输入特性的动态可重构Dither结构

将伪随机数的宽带大幅度Dther(抖动)技术应用于高速、高精度A/D转换器(ADC)中,能够将量化噪声随机化,提高ADC的分辨率,在统计意义上减小微分非线性(DNL)误差,改善ADC的动态性能.针时流水线型ADC结构,根据各个子ADC输入信号的特点,提出动态可重构宽带大幅度Dither结构.将大幅度Dither分别引入ADC芯片内部各个子ADC中,在改善ADC动态性能的同时,使Dither动态调整更加灵活且有针对性,降低了Dither结构中DAC的位数和功耗.