Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.     

Impact of geometry on stretchable meandered interconnect uniaxial tensile extension fatigue reliability

This work investigates the impact of geometry on the reliability of a high conductivity, meandered, stretchable interconnect. Meandered copper conductor interconnects of varying geometries that have been encapsulated into a PDMS matrix, are evaluated for reliability under tensile stretching conditions to 10% elongation. We present results that support our earlier findings by experiment and FEM simulation. Following, we vary interconnect parameters related to the encapsulation geometry, such as encapsulation hardness, thickness and stretchable zone perimeter, to assess impact on fatigue life of the embedded meandered copper lines. Results confirm and refine the prior simulation findings. Combinations of interconnect geometry parameters critical for stretching reliability are identified. Among others, we find that the meander radius (R) and encapsulation thickness are strongly coupled, causing very large meanders with thick encapsulation to fail very early. We show that, depending on the design of the meander transition, the characteristic life of an interconnect can differ 50 times under moderate, 10% cyclic elongation. Finally, we indicate the significance of our findings for the design of reliable, stretchable electronic systems.     

矿业经济,技术预测决策的系统研究

本文对矿业经济、技术预测决策的系统研究进行了整体设计，并运用某大型采选联合铜矿企业历年的生产数据，建立了有关的灰色预测决策模型。结果表明灰色系统理论在矿业系统的经济、技术研究中的应用是有效的。     

大气等离子喷涂制备SOFC连接体Cu/Mn/Co金属防护涂层

为了进一步提高固体氧化物燃料电池（SOFC）连接体防护涂层的电导率,采用大气等离子喷涂技术（APS）制备了Cu/Mn/Co金属涂层．研究了不同喷涂工艺参数对涂层性能的影响,以及涂层在800 ℃下的氧化行为．通过XRD,SEM及EDS表征涂层高温氧化过程中的相结构、表面形貌和微观结构演变,采用直流四电极法测量涂层的高温电导率．结果表明,800 ℃下氧化使金属涂层转变成了MnCo₂O₄/Cu_xMn_3-xO₄相．氧化初期,涂层表面和底部出现富Cu层;随氧化时间增加,富Cu层逐渐消失,Cu元素均匀分布在涂层中;当氧化120 h时,涂层表层的CuO层已不连续,与涂层分层且产生微裂纹．同时发现,长时间氧化后涂层截面明显致密化,形成了顶部致密、底部多孔的结构．此外,电流为550 A的涂层试样（No.2）尖晶石相最多,涂层致密度最高,其电导率也最高．800 ℃下氧化120 h后,电流为500,550和600 A的三种涂层试样（No.1~No.3）电导率分别为59.68S,93.55和85.72 S/cm,并且氧化过程中电导率保持稳定．所制备的金属涂层和尖晶石涂层均表现出较好的阻Cr扩散效果,Cr主要以Cr₂O₃的形式富集在基体和涂层的结合处．      

数据传输系统的可编程逻辑技术实现

本文介绍了数据传输系统体系结构的设计方法，主要针对数据传输系统进行设计，详细论述了系统的总体设计、模块设计、PCI（Peripheral Component Interconnect外围部件互连）总线高速数据传输系统硬件接口设计方法,给出了系统的设计与实现方案。克服了系统中的有关数据传输速率、可靠性等方面的问题，提高了数据传输过程中抗干扰能力     

互联电网接入IPC参数调整时刻的研究

模拟两侧电网通过一点互联，在一侧电网端口接入IPC。在对两侧复杂电网进行简化等值基础上，建立IPC通用电路模型，并进行向量分析。选择IPC电容器、电抗器的参数调整时间，对调控过程中IPC电容器的电流冲击和电抗器的电压冲击进行有效抑制。     

ULSI多层互连中的化学机械抛光工艺

介绍了化学机械抛光(CMP)技术在大规模集成电路多层互连工艺[1]中的重要作用,对CMP过程和CMP的影响因素进行简单分析。总结出CMP技术在多层互联平坦化中的优势,介绍目前常用互连材料中SiO2介质及其金属材料钨和铜的化学机械抛光常用分析机理,并简单介绍了各种互联材料常用的抛光液及抛光液的组分,对抛光液作了简单的对比。针对传统CMP过程存在的问题,分析了皮带式和固定磨料的CMP技术。     

提高成品率的VLSI互连线线宽优化

金属互连线层的设计对VLSI成品率有着重要影响 .研究了制造缺陷与互连线层成品率的关系 ,通过关键面积概念说明了在有制造缺陷影响的情况下 ,互连线线宽参数对成品率的影响 .提出了一种基于线宽调整以期降低互连线缺陷关键面积、从而提高成品率的优化模型和算法 ,并通过 4× 4移位寄存器版图单元的线宽优化实例说明了这种互连线宽优化方法能有效提高成品率 .优化实例表明 ,线宽调整能够引起VLSI的开路和短路关键面积发生变化 .在设计规则容许范围内 ,根据实际版图的关键面积特点对互连线线宽进行优化 ,可以降低芯片对制造缺陷的敏感程度 ,从而提高制造成品率     

高层次综合中的互连单元分配算法

首先对高层次综合中的互连单元分配进行了讨论，引入数据通路连接图的表示模型，定义了标准寄存器单元、标准型数据通路及数据通路连接图的形式化描述。在此基础上给出了一个互连单元分配算法IU-Al-location。经对实例和典型及相关数字电路进行试验后分析，本算法效率高、速度快，取得了较好的结果。