开关电源交错拓扑输出电流纹波数学分析

本文首次提出运用线性函数和组合波形原理，推导开关电源任意N通道交错并联拓扑输出电流纹波幅值与单通道占空比关系的数学模型，根据数学模型可以定量表达任意N通道交错并联拓扑输出电流纹波幅值大小，为设计具有最优输出电流纹波特性的交错并联拓扑奠定了理论基础。     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.     

液压开关回路的基本结构

运用作者在有关文献中提出的单通道液压开关理论，从液压执行元件入手，经过分析与讨论，提出了液压开关回路的最简结构和实用结构其原理有助于液压件及液压系统设计与制造的标准化、系列化     

山东电网部分500 kV线路不平衡电流偏大原因的分析及改善措施的研究

针对山东电网部分500 kV线路的局部电流不平衡现象,通过仿真模拟了系统运行中的大(上午10:00)、小(凌晨3:00)潮流方式下的电流不平衡现象,并与电网运行中实测积累的大量不平衡电流数据进行比较,找出500 kV系统局部产生不平衡电流的原因是线路参数不平衡,即淄川-益都-潍坊同塔双回线路全线不换位及多条不平衡线路构成的2个环网,使个别线路在一定条件下产生了严重的不平衡电流。为改善该不平衡现象,对22种同塔双回线路的导线排列方式进行模拟计算分析,得出优化的导线排列组合方式。模拟计算结果表明,通过在变电站出线处合理调整同塔双回线路的导线排列方式,可有效改善山东500kV系统的局部电流不平衡现象。     

异步电路验证算法

异步电路因不受时钟偏差的限制而逐渐成为电路设计研究的热点 .发展自动化的验证工具已成为确保大规模异步电路质量和性能的关键 .其核心课题就是建立异步电路的验证算法 .该文整理列举了基于多种数学模型的验证算法 ,如逻辑模型、代数模型、符号模型、数值模型和几何模型的验证算法 ,并从应用的角度将现有的异步电路验证算法分为两类 ,分别是事件时序分析类算法和状态空间搜索类算法 ,从算法的理论基础、应用背景、模型结构、图形描述、适用范围、算法复杂度编程复杂度等多个角度作了比较研究 ,给出了部分代表算法的应用算例 ,最后总结了在实际问题中选择验证算法的原则     

基于Multisim的电路仿真分析与设计

Multisim是知名的EDA软件之一，内含数万种元器件和13种常用的虚拟仪嚣仪表。用它可以方便地搭接各种电工电子电路，准确地对电路进行仿真分析。通过几个电路设计实例的仿真分析，说明使用Multisim软件进行电路设计，不仅可以提高设计效率，而且可以保证设计质量。     

基于多目标自适应遗传算法的逻辑电路门级进化方法

提出一种改进的遗传算法，通过网表级编码、多目标评估和遗传参数自适应等措施，可依据多个设计目标，以较少的运算量自动生成和优化逻辑电路．在数字乘法器、偶校验器等进化设计实验中，通过比手工设计和同类方法更优的新奇设计结果展示了该方法的有效性和先进性．     

Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits

In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.     

An interval algorithm for finding all solutions of non‐linear resistive circuits

In this letter, an efficient algorithm is proposed for finding all solutions of non‐linear (not piecewise‐linear) resistive circuits. This algorithm is based on interval analysis, the dual simplex method, and the contraction methods. By numerical examples, it is shown that the proposed algorithm could find all solutions of systems of 500–700 non‐linear circuit equations in acceptable computation time. Copyright © 2004 John Wiley & Sons, Ltd.     

Linear bipolar OTAs employing exponential‐law circuits

This paper presents design of linear bipolar OTAs, which are composed of two function blocks; one is an exponential‐law circuit and the other is a core cell. Multi‐tanh cells are employed as the core cell. This kind of OTA has lower power dissipation relatively to the conventional multi‐tanh cell. According as the order of the multi‐tanh core cell becomes higher, the number of circuit realization for the core cell increases. For example, we have two OTAs for the core circuit of an emitter‐coupled pair and four OTAs for the doublet core cell. Thus, we consider the generalized OTAs for an arbitrary order n of the core cell and obtain a formula to give the realization number of the linear OTAs for n. According to the formula, there must be eight OTAs in the case of n=3. All of the eight OTAs are examined. Analysis and simulation results show that the OTAs have advantage in their characteristics, such as linear input range, power dissipation, noise, and frequency response. Copyright 2004 John Wiley & Sons, Ltd.