Partial scan flip-flop selection by use of empirical testability

Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan flip-flop selection method proposed here is to obtain maximum fault coverage for the number of scan flip-flops selected. Empirical Testability Difference (ETD), a measure of potential improvement in the testability of the circuit, is used to successively select one or more flip-flops for addition or deletion of scan logic. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the acutal automatic test pattern generation (ATPG) system. In addition, once such faults are known, ETD focuses on the hard-to-detect faults rather than all faults and uses heuristics to permit effective selection of multiple flip-flops without global optimization. Two ETD algorithms have been extensively tested by using FASTEST ATPG [1, 2] on fourteen of the ISCAS89 [3] sequential circuits. The results of these tests indicate that ETD yields, on average, 35% fewer uncovered detectable faults for the same number of scanned flip-flops or 27% fewer scanned flip-flops for comparable fault coverage relative to cycle-breaking methods.This work was performed while the author was with the University of Wisconsin-Madison.     

基于解释结构模型的装备测试性影响因素分析方法

通过对装备测试性水平的相关影响因素分析,构建解释结构模型,探求各装备测试性影响因素间的关联性,运用“手段-目的分析”方法识别出影响装备测试性的5个关键影响因素,并通过对装备系统复杂程度、研制方技术及管理水平、研制经费、测试分系统间接口兼容性以及测试点选择合理性的分析,为提高装备测试性水平提供对策建议。     

Recognizing authors: an examination of the consistent programmer hypothesis

Software developers have individual styles of programming. This paper empirically examines the validity of the consistent programmer hypothesis: that a facet or set of facets exist that can be used to recognize the author of a given program based on programming style. The paper further postulates that the programming style means that different test strategies work better for some programmers (or programming styles) than for others. For example, all‐edges adequate tests may detect faults for programs written by Programmer A better than for those written by Programmer B. This has several useful applications: to help detect plagiarism/copyright violation of source code, to help improve the practical application of software testing, and to help pursue specific rogue programmers of malicious code and source code viruses. This paper investigates this concept by experimentally examining whether particular facets of the program can be used to identify programmers and whether testing strategies can be reasonably associated with specific programmers. Copyright © 2009 John Wiley & Sons, Ltd.     

Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations

Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.

改进的故障分辨率计算公式和序替代方法

故障分辨率是复杂电子系统的一个重要测试性指标,传统的计算故障分辨率的公式只适用于系统中所有元件(或模块)都服从指数分布的情况.事实上,正态分布、威布尔分布和指数分布都是常用的失效分布.鉴于此,本文提出了一个适用于各种失效分布的故障分辨率计算公式;然后在充分利用各模块历史维护数据和分布函数的基础上提出了一种优化替代次序的方法.理论分析和仿真结果证明本文的方法有如下现实价值:节省设计和生产成本;减少系统维护预算;降低系统维修时间和费用.     

电子装备测试性融合评估方法

测试性是装备通用质量特性之一，其设计水平直接影响了装备保障效能的发挥，如何更加真实的评估装备的测试性水平是当前研究的热点。在研制阶段装备实物测试性试验数据数量少、获取难、费用高，可认为是“小子样”数据，为了更加全面客观地评价装备的测试性水平，需要充分利用测试性仿真试验获取仿真数据进行融合评估。进行测试性仿真试验时，研究电子装备的仿真模型、故障模型、仿真故障注入方法，获取测试性仿真数据；在此基础上，将仿真试验数据作为验前信息并进行的处理，结合“小子样”装备实物试验数据，采用贝叶斯方法进行测试性试验数据的融合来评估装备的测试性水平，提高评估结果的客观性和可信度。通过案例分析，验证了测试性融合评估方法的有效性。     

Test sample allocation method for testability verification test

An extended failure mode effect and criticality analysis (FMECA)-based sample allocation method for testability verification is presented in this study to deal with the poor representativeness of test sample sets and the randomness of the testability evaluation results caused by unreasonable selection of failure samples. First, the fault propagation intensity is introduced as part of the extended information of FMECA, and the sample allocation impact factors of component units and failure modes are determined under this framework. Then, the failure mode similarity and impact factor support are defined, and the game decision method for weighing the relationship between similarity and support is proposed to obtain the weight of failure mode impact factor. Finally, a two-step allocation framework of test samples is formulated to realize the sample allocation of component units and failure modes. This method is applied to the testability verification test of a launch control system. Results show that this method can obtain more representative test samples compared with the traditional sample allocation method while effectively reducing randomness of single testability evaluation result.     

基于改进离散粒子群算法的传感器优化配置

传感器优化配置是实现航空设备故障预测与健康管理(Prognostics and Health Management,PHM)系统设计的基础和保证.本文首先对系统的故障-传感器相关性矩阵进行了改进,在此基础上根据系统测试性指标要求建立了考虑传感器故障率的约束优化模型,并采用一种改进的离散粒子群算法求解.算法根据传感器优化配置的特点设计了粒子个体适应度计算方法,惯性权重则基于群体早熟程度自适应调整.仿真实例验证了本文方法的有效性,优化结果满足系统各项测试性指标要求,可为航空设备PHM系统的传感器优化配置提供有效指导.     

学习策略实现的条件和加法器通路时延故障测试生成

时延故障对高速运算电路性能有着关键性的影响，本文对高速加法器之一的条件和加法器的通路时延故障作了研究。首先对其提出了一种可测性设计，主要特点是硬件成本低和测试向量少，且实现了完全的无险象强健时延故障可测性。在此基础上，进一步提出了一种学习策略的方法，实现了任意位数条件和加法器通路时延故障的测试生成，使得测试难度下降，测试时间缩短，测试效率提高。仿真实验结果表明了该方案的有效性。