IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.     

A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards

Huffman coding is a popular and important lossless compression scheme for various multimedia applications. This paper presents a low-latency parallel Huffman decoding technique with efficient memory usage for multimedia standards. First, the multi-layer prefix grouping technique is proposed for sub-group partition. It exploits the prefix characteristic in Huffman codewords to solve the problem of table size explosion. Second, a two-level table lookup approach is introduced which can promptly branch to the correct sub-group by level-1 table lookup and decode the symbols by level-2 table lookup. Third, two optimization approaches are developed; one is to reduce the branch cycles and the other is parallel processing between two-level table lookup and direct table lookup approaches to fully utilize the advantage of VLIW parallel processing. An AAC Huffman decoding example is realized on the Parallel Architecture Core DSP (PAC DSP) processor. The simulation results show that the proposed method can further improve about 89% of decoding cycles and 33% of table size comparing to the linear search method.

自适应运行时可重构缓存优化

动态可重构缓存由于能够在运行时进行缓存容量、结构、映射规则等方面的重新配置,因而在资源利用率和能耗方面有很大优势。针对超长指令字处理器发射宽度动态变化的特点,提出了在运行时利用其动态特征来驱动缓存的重构,从而达到动态分离或合并处理器核的目的。这不同于传统的以缓存缺失率来驱动缓存重构的方法。为了平滑频繁重构场景下缓存的性能,进一步提出了一种重构时的过渡机制,使缓存平滑地从一种配置过渡到另一种配置。设计了实验并对重构策略进行了性能评估,仿真结果表明,该方法可以实现在重构后2 000周期内,缓存缺失率平均下降16%,并且提高了系统性能。     

A scalable and low power VLIW DSP core for embedded system design

Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set （VLES） execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to execute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less number of functional units according to the intended application. Low power support was added by careful architectural design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations, especially for compute intensive applications such as wire-line and wireless communications, including infrastructure and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effectively reduce the power consumption, chip area and time to market the intended final product.     

数字信号处理器分布式寄存器的写回设计

针对分布式寄存器文件应用于高性能超长指令字（VLIW）数字信号处理器而造成的分支流水线与写回控制信号的同步问题,提出了一种面向分布式本地寄存器文件的写回策略。其中包括指令执行周期的产生,写回信号缓存以及写回控制单元。采用了面积功耗性能评估方法,结果证明了该策略能充分发挥分布式寄存器文件在功耗方面的优势,相对于运用集中式寄存器文件可以减少50％的功耗,同时对于传统流水线写回控制方法可以节省60％的面积开销。     

BWDSP100数字信号处理器的指令缓存器设计

本文介绍了一种应用于高性能数字信号处理器BWDSP100的指令缓存器。该指令缓存器支持超长指令字,共有三级缓冲,每级缓冲包含16个指令槽。该指令缓存器可高效完成指令执行行的提取、拼接及废弃等操作,可有效提高DSP的指令执行效率。     

基于甚长指令字处理器的启发式手动编码方法

虽然有针对VLIW处理器的复杂编译器,但是通过手动汇编能够更有效地实现这些算法。手动编码是一项易出错,耗时的工作。为了解决这个问题,文章提出了一种手动编码的启发式实现方法,相对于单纯的手动编码,它能够在更短的时间内更有效地实现算法。在德州仪器的VLIW处理器TMS320C6x上,使用这种方法实现了IIR滤波器算法,证实了其有效性。     

GCC的流水冲突识别器和并行调度器

由于超长指令字处理器通常都有多级流水线和复杂的资源使用限制,如何准确地描述处理器的流水线模型,快速地判断是否存在资源冲突并不是个简单地任务。文章介绍GCC新引入的正则表达式语法的流水线描述机制。在将GCC移植到笔者所开发的SuperV芯片的过程中,利用该机制对SuperV芯片的流水线结构和资源使用限制进行详尽地描述,启动了GCC的指令级并行调度。通过并行调度,测试程序的性能提高了大约6%—35%。     

VLIW微处理器特征与编译技术支持

VLIW是一种早已出现但一直未能广泛使用而现今又被重新重点研究的微处理器设计思想与技术，它跟超标量技术一样支持每周期执行多条指令，但并行度更高。本文将详细介绍VLIW的概念及其发展历程，讨论VLIW微处理器的特征与所需的编译技术支持，并与超标量微处理器进行比较分析。