Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

基于对比折射法的三维静校正技术及其应用

在地形起伏剧烈、速度和厚度横向变化大的地区，折射静校正技术的应用受到诸多限制，主要表现在不能准确地识别和拾取来自于地下连续地质界面的折射波，使得精确求取的长波长静校正量困难。为此，提出了一种基于对比折射法的三维静校正技术。介绍了这种静校正技术的方法原理和特点，基于对比折射法的折射波至拾取实质上是一个折射层的对比分析解释过程，因此能准确地拾取折射波至，精确地求解低速带的绝对延迟时；然后利用延迟时和近地表速度模型（等效，时深，空变）反演表层模型，最终一次性完成基准面静校正（包含低速带校正和高程校正）。在黄土塬、沙漠以及沙漠和山地的接合部等地区，利用基于对比折射法的三维静校正技术进行静校正处理，使资料的品质得到了明显改善，反射同相轴连续性好，信噪比和分辨率高，构造形态清晰可靠，提高了勘探精度。     

基于光纤环的光缓存器

提出了一种基于光纤环的光缓存器的结构,对结合半导体光放大器作光开关的此结构的物理模型进行了详细描述,并根据此模型分析了其增益、噪声、信噪比等方面的特性.     

地震数据采集系统延迟时间研究与分析

文章分析了影响地震采集系统延迟时间的因素,并根据系统延迟的理论对产生的原因进行了论证.同时对实际生产中的测试方法进行了阐述研究和分析,提出了新的测试方法,并结合实际生产提出了合理性建议.     

Performance characteristics of cascaded delay‐line node architectures in single‐path interconnection networks

Internally buffered multistage interconnection network architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded fibre delay line architectures can be seen as possible realizations of output and shared buffering in a 2 × 2‐switching element. These approaches can be used as buffered node architecture in a Banyan like interconnect. In this paper, we investigate and compare these approaches by using simulation methods. Different performance metrics, such as normalized throughput, average packet delay, packet loss rate and buffer utilization have been used under uniform and non‐uniform traffic models. Results show that the TC‐chain node Banyan network offer an improved normalized throughput and average packet delay performances under both traffic models without disrupting first‐in‐first‐out order of arrivals. The switched delay‐line requires fewer switching elements than TC and TTC architectures but at the cost of high packet delay. Copyright © 2004 John Wiley & Sons, Ltd.     

CMOS缓冲器的时延估算模型

随着集成电路生产工艺的进展，互连线在集成电路设计中的影响越来越大。为了减小互连线的影响，通常在芯片互连中插入缓冲器，但这样做会增加时延。因此，为了精确地对系统进行时延估计，必须对缓冲器的时延进行估算。基于Sakurai的器件模型，提出了一种新的缓冲器时延估算模型。     

DMT系统中一种易于实现的时域均衡器

总结了DMT系统中时域均衡器(TEQ)的主要设计方法，指出最大缩短信噪比(MSSNR)TEQ的最优设计方法很难实时实现。提出了一种MSSNR TEQ的次优设计方法，它首先估计出目标抽样窗的最优延迟，然后用分步求解法求出TEQ的抽头系数。和最优方法相比，次优方法的计算量大幅度减少，可实时实现，而其缩短信噪比的损失很小。仿真实验验证了次优方法的有效性。     

SAW软扩频调制解调器的研究

报道了一种直接序列软扩频调制解调器的SAW实现方案，并给出了相应的实验结果。该方案对提高系统抗干扰能力、频宽利用等方面均具有与其他技术不同的特点。同时，该技术方案为进一步研究DS-OFDM打下了基础。     

微波体声波延迟线的电磁屏蔽

本文分析了微波体声波延迟线多层介质的电磁屏蔽效应，结果表明，全屏蔽方式可以有效地解决微波延迟线研制中的直通抑制问题。实验结果证实了理论分析。     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.