Reconfigurable hardware implementation of a phase-correlation stereoalgorithm

This paper describes the implementation of a stereo-vision system using Field Programmable Gate Arrays (FPGAs). Reconfigurable hardware, including FPGAs, is an attractive platform for implementing vision algorithms due to its ability to exploit parallelism often found in these algorithms, and due to the speed with which applications can be developed as compared to hardware. The system outputs 8-bit, subpixel disparity estimates for 256× 360 pixel images at 30,fps. A local-weighted phase correlation algorithm for stereo disparity [Fleet, D. J.: {Int. Conf. Syst. Man Cybernetics 1:48–54 (1994)] is implemented. Despite the complexity of performing correlations on multiscale, multiorientation phase data, the system runs as much as 300 times faster in hardware than its software implementation. This paper describes the hardware platform used, the algorithm, and the issues encountered during its hardware implementation. Of particular interest is the implementation of multiscale, steerable filters, which are widely used in computer vision algorithms. Several trade-offs (reducing the number of filter orientations from three to two, using fixed-point computation, changing the location of one localized low-pass filter, and using L1 instead of L2 norms) were required to both fit the design into the available hardware and to achieve video-rate processing. Finally, results from the system are given both for synthetic data sets as well as several standard stereo-pair test images.     

企业中层管理人员培训的思考

以分析企业中层管理人员培训的现状为突破口,阐述了中层管理人员培训需求分析的思路和方法。在此基础上对培训内容进行整体设计,指出针对此类培训应采用的培训方式和评估方法。以期对企业中层管理人员的培训起到一些启发和借鉴作用。     

浅析FIPS PUB 140-2标准

论文简单分析了FIPSPUB140-2标准及其在密码模块开发过程中的指导意义,可作为密码模块技术开发人员在进行安全性设计时的参考。     

基于支持向量机的缓存预估模型的设计与实现

采用支持向量机(SVM)对网络业务流数据进行预测估计，通过训练样本，从而获得样本以外数据的分布规律。在此基础上，设计了一种网络排队队列缓存的预估模型。实验表明，该模型具有较高的训练效率和很高的估计精确度。     

Night and Day: Are Siblings as Different in Temperament as Parents Say They Are?

Twin studies suggest that parent ratings of temperament exaggerate differences between twins. The present study examined whether such contrast effects also operate for nontwin siblings. The activity level (AL) and shyness of 95 nontwin sibling pairs (ages 3 to 8 years) were assessed via parent ratings and objective measures (actigraph and observer ratings). Siblings showed no resemblance in either parent-rated AL or shyness; however, sibling resemblance for actigraph AL and observer-rated shyness was substantial. Thus, parents do contrast their nontwin siblings when rating these 2 temperament dimensions. Moreover, the importance of sibling differences in temperament to the sibling relationship and differential maternal treatment varied across the different measures of AL and shyness, suggesting that parent perceptions may play a role in these associations. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Cable Modem的原理与反向噪声的控制

介绍Cable Modem的基本概念、传输方式、标准规范，并对影响Cable Modem工作稳定性的反向噪声问题进行技术分析，并提出预防控制措施。     

多级非线性加权平均中值滤波改进算法

介绍了中值滤波的概念和几种改进的中值滤波算法，在几种改进算法的基础上提出了新的中值滤波改进算法。依据以上几种算法进行了仿真试验和图像视觉上的比较，并进行了数字图像的峰值信噪比（PSNR），归一化均方误差（NMSE）和归一化平均绝对误差（NMAE）的几种定量指标的比较。实验结果和几种定量指标比较结果表明，该算法能有效地滤除图像中的椒盐噪声，还能使图像保持很好的清晰度，明显优于几种改进的中值滤波算法。     

异步DS-CDMA系统中基于矩阵点除算法的DOA估计

针对异步DS-CDMA系统中的多用户环境,本文提出了一种低复杂度的DOA估计算法——矩阵点除算法。该算法通过对感兴趣信息的逐次分离,实现了DOA的逐路径估计。算法具有两方面显著优势:(1)克服了传统的DOA估计算法在路径总数大于天线阵元数时不能工作这一缺陷:(2)避免了计算复杂的特征值分解运算,大大降低了算法复杂度。仿真实验验证了算法的有效性。     

V波段小型化低相噪频率综合器

本文研究了一种V波段超小型低相噪频率综合器,研制了L段捷变频频综、Ku波段取样锁相源、上变频组件、倍频器等四个小型化组件.为了得到较低的相位噪声和捷变频速度,本捷变频频综采用上变频-倍频方案,其中DRO PLS保证低相位噪声性能,L波段捷变频频综保证捷变频功能.该频综尺寸为100×80×30mm³,相位噪声低于-86dBc/Hz(1kHz),捷变频时间小于40μs,杂波抑制优于-60dBc.     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.