Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

计算机高速并行通信的实现方案

利用CPLD芯片实现单片机与ISA总线接口之间的高速并行通信，给出系统的总体设计方法及程序框图。采用这种通信方式，在12MHz晶振的MCS51单片机控制的数据采集系统中，可以满足与PCI04 ISA总线接口实时通信的要求，通信速率达200khit／s。在开发工具MAX plusⅡ下，完成了整个设计的输入、编译和仿真，达到了预期效果。本设计方案能够推广应用到计算机的高速并行通信中。     

多码CDMA系统中联合并行干扰抵消与迭代信道估计方法

本文针对多码CDMA系统提出了一种联合并行干扰抵消与迭代信道估计方法。该方法首先通过导频符号对信道进行估计，然后使用RAKE接收机后的软信息对信道参数进行修正，最后通过并行干扰抵消(PIC)去除多码干扰(MCI)。仿真结果表明，经过多次迭代后，该方法可显著地降低多码CDMA系统的误比特率平台。本文同时还给出了信道估计质量、码道数和PIC次数对多码CDMA系统性能的影响。     

Mesh结构P/G布线网络层次化快速分析方法

本文提出了一个基于网络划分的P／G布线网络层次化快速分析方法。其中，对于子网运算，通过对Cholesky分解法三角化对称正定阵的图模型分析，并基于Mesh结构网络的自身特点，提出了一个基于图顶点排序的加速子网分析运算策略；并用基于MPI的并行结构实现了P／G布线网络分析的并行运算。     

Serial deployment of attention during visual search.

This study examined whether objects are attended in serial or in parallel during a demanding visual search task. A component of the event-related potential waveform, the N2pc wave, was used as a continuous measure of the allocation of attention to possible targets in the search arrays. Experiment 1 demonstrated that the relative allocation of attention shifts rapidly, favoring one item and then another. In Experiment 2, a paradigm was used that made it possible to track the absolute allocation of attention to individual items. This experiment showed that attention was allocated to one object for 100-150 ms before attention began to be allocated to the next object. These findings support models of attention that posit serial processing in demanding visual search tasks. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Windows 95/98环境下PC机并行打印端口控制步进电机的研究

介绍了在Windows95／98环境下利用IBM-PC机打印端口控制步进电机运动的实现方法，并给出了关键程序的实现代码。     

智能工作站主机的MMPIS实验模型研究──一个全互连式结构MMPIS硬件环境的设计与实现

本文介绍中日国际合作开发研究的Ａ１型智能网（Ａ１型ＩＮ）智能工作站（ＩＷ）主机的并行推理硬件结构的实验模型设计与实现，给出了一种并行推理硬件支持环境实现方案和该方案在实现中若干问题的解决方法。     

货郎担问题最优并行启发式算法

本文给出了满足三角不等式的货郎担问题的并行启发式算法，在ＳＩＭＤ ＣＲＥＶ ＰＲＡＭ并行机上该算法使用Ｏ（ｎ＾３／ｌｏｇ＾２ｎ）台处理器需Ｏ熄ｌｏｇ＾２ｎ）时间，这里ｎ是给定城市的个数，因而该并行算法是最优的。