The Effect of the Estimation on Goodness‐of‐Fit Tests in Time Series Models

Abstract. We analyze, by simulation, the finite‐sample properties of goodness‐of‐fit tests based on residual autocorrelation coefficients (simple and partial) obtained using different estimators frequently used in the analysis of autoregressive moving‐average time‐series models. The estimators considered are unconditional least squares, maximum likelihood and conditional least squares. The results suggest that although the tests based on these estimators are asymptotically equivalent for particular models and parameter values, their sampling properties for samples of the size commonly found in economic applications can differ substantially, because of differences in both finite‐sample estimation efficiencies and residual regeneration methods.     

Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

Education-driven research in CAD

We argue for a new research category, named education-driven research (EDR), which fills the gap between traditional field-specific research that is not concerned with educational objectives and research in education that focuses on fundamental teaching and learning principles and possibly on their customization to broad areas (such as mathematics or physics), but not to specific disciplines (such as CAD). The objective of EDR is to simplify the formulation of the underlying theoretical foundations and of specific tools and solutions in a specialized domain, so as to make them easy to understand and internalize. As such, EDR is a difficult and genuine research activity, which requires a deep understanding of the specific field and can rarely be carried out by generalists with primary expertise in broad education principles. We illustrate the concept of EDR with three examples in CAD: (1) the Split and Tweak subdivisions of a polygon and its use for generating curves, surfaces, and animations; (2) the construction of a topological partition of a plane induced by an arbitrary arrangement of edges; and (3) a romantic definition of the minimal and Hausdorff distances. These examples demonstrate the value of using analogies, of introducing evocative terminology, and of synthesizing the simplest fundamental building blocks. The intuitive understanding provided by EDR enables the students (and even the instructor) to better appreciate the limitations of a particular solution and to explore alternatives. In particular, in these examples, EDR has allowed the author to: (1) reduce the cost of evaluating a cubic B-spline curve; (2) develop a new subdivision curve that is better approximated by its control polygon than either a cubic B-spline or an interpolating 4-point subdivision curve; (3) discover how a circuit inclusion tree may be used for identifying the faces in an arrangement; and (4) rectify a common misconception about the computation of the Hausdorff error between triangle meshes. We invite the scientific community to encourage the development of EDR by publishing its results as genuine research contributions in peer-reviewed professional journals.     

Neural network systems to reproduce crash behavior of structural components

The use of neural networks as global approximation tool in crashworthiness problems is here investigated. Neural networks are not only asked to return some meaningful indices of the structural behavior but also to reproduce load-time curves during crash phenomena. To contain the number of examples required for the training process, parallel subsystems of small neural networks are designed. Design points for the training process are obtained by explicit finite element analyses performed by PAMCRASH. The settlement of the points in the design domain is defined using a maximum distance concept. The procedure is applied to different typical absorption structures made of aluminum alloy: riveted tubes, honeycomb structures, longitudinal keel beam and intersection elements of helicopter subfloors.     

计算机高速并行通信的实现方案

利用CPLD芯片实现单片机与ISA总线接口之间的高速并行通信，给出系统的总体设计方法及程序框图。采用这种通信方式，在12MHz晶振的MCS51单片机控制的数据采集系统中，可以满足与PCI04 ISA总线接口实时通信的要求，通信速率达200khit／s。在开发工具MAX plusⅡ下，完成了整个设计的输入、编译和仿真，达到了预期效果。本设计方案能够推广应用到计算机的高速并行通信中。     

多码CDMA系统中联合并行干扰抵消与迭代信道估计方法

本文针对多码CDMA系统提出了一种联合并行干扰抵消与迭代信道估计方法。该方法首先通过导频符号对信道进行估计，然后使用RAKE接收机后的软信息对信道参数进行修正，最后通过并行干扰抵消(PIC)去除多码干扰(MCI)。仿真结果表明，经过多次迭代后，该方法可显著地降低多码CDMA系统的误比特率平台。本文同时还给出了信道估计质量、码道数和PIC次数对多码CDMA系统性能的影响。     

Mesh结构P/G布线网络层次化快速分析方法

本文提出了一个基于网络划分的P／G布线网络层次化快速分析方法。其中，对于子网运算，通过对Cholesky分解法三角化对称正定阵的图模型分析，并基于Mesh结构网络的自身特点，提出了一个基于图顶点排序的加速子网分析运算策略；并用基于MPI的并行结构实现了P／G布线网络分析的并行运算。