具有自动频率校准的宽频率范围Σ-Δ小数频率综合器

A wide range fractional-N frequency synthesizer in 0.18μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range.A 16-bit third-order sigma-delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm~2.The experimental results show the proposed frequency synthesizer consumes 4.3 raA from a single 1.8 V supply voltage except for buffers.The frequency range is 1.44-2.11 GHz and the frequency resolution is less than 0.4 kHz.The phase noise is -94 dBc/Hz @ 100 kHz and -121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz.The performance meets the requirements for the multi-band and multi-mode transceiver applications.     

高速高精度流水线模数转换器的设计

本文给出了两版基于0.18mmCMOS工艺的12位100MS/s流水线ADC。测试、分析了两版芯片,经过改进版图得到满意结果。     

SFDR高于100dB的14位欠采样循环模数转换器

本文为射频标签(RFID)收发机系统设计了一个高线性,14位357 k采样率的欠采样循环模数转换器。为提高模数转换器的精度,设计中采用了有源电容误差平均(PCEA)技术。并且提出了一种改进的PCEA采样网络,可以消除两个流水级之间的串扰影响。为降低模数转换器的功耗和减小面积,设计采用了运放共享技术,并且去除了采样保持放大级。为补偿不完善的版图设计引入的误差,增加了一个附加的数字校准模块。该模数转换器由180 nm CMOS工艺流水完成,面积为0.65 mm  1.6 mm。在确保SFDR不低于90 dB的条件下,该欠采样模数转换器的输入信号频率高达15.5 MHz;在2.431 MHz输入下,峰值SFDR高达106.4 dB.     

A 13-bit, 8 MSample/s pipeline A/D converter

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm IP6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm2, including I/O pads.     

应用于人工关节无线监控系统的低功耗循环式ADC设计

This paper presents a low power cyclic analog-to-digital convertor （ADC） design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks （MDACs） and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully op- timized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation （UMC） 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.     

一种适用于流水线ADC的数字校准算法的硬件实现

研究了一种适用于开关电容级电路结构的流水线ADC的数字后台校准算法并提出了其硬件实现方法.此算法适用于每级1.5bit和多bit的子级转换电路,实时地监控关键子级电路转换函数的特性,并从数字输出中提取校准信息,不中断正常的转换过程.文中提出的硬件实现方法通过有限状态机实现该算法,实现了各模块高效的协同工作.仿真证明用该硬件实现方法设计的校准处理系统能够有效校准电容失配和运放有限增益误差.     

二维稳态热传导热源反问题LS-SVM解

本文研究了一类二维稳态热传导热源反问题．首先设置训练点集,将问题的近似解表示为与训练点集相关的高斯核函数组合的形式,然后依据最小二乘支持向量机原理优化参数．近似解由两部分组成,第一部分为满足边界条件的已知函数;第二部分为两项乘积,其中一项为在边界上为零的已知函数,另一项为含回归参数核函数线性组合形式．最后,通过两个有解析解的算例检验方法的有效性．结果表明了本文方法用于研究二维稳态热传导热源反问题的可行性．     

13 bit 50 MS/s CMOS流水线ADC的设计

介绍了一种新的流水线ADC校准算法,并利用该校准算法完成了一个13 bit,50 MS/s流水线ADC的设计.该校准算法对级电路的比较器和后级电路的输出码字的出现频率进行统计,得到各个级电路输出位的真实权值,可以同时校准多种非理想因素如运放有限增益、电容失配等造成的误差.电路采用UMC 0.18μm混合工艺,1.8 V电源电压.通过SPECTRE仿真获得晶体管级级电路的输入输出关系,将其结果导入顶层行为级模型进行校准.仿真结果表明,在50 MHz采样率、5 MHz输入信号下,通过校准算法SFDR由44.1 dB提升至102.2 dB,SNDR由40.9 dB提升至79.9 dB,ENOB由6.5 bit提升至12.98 bit.     

基于0.18μm CMOS工艺的多标准射频滤波器

采用UMC 0.18μm CMOS工艺,实现了一个Q值增强型LC多标准射频滤波器;实现中心频率以及带宽的连续可调,以适合不同通信标准的要求;采用LNA作为输入级,考察了噪声抵消机制,实现了较低的噪声系数(NF≤6 dB)及良好的输入输出匹配特性.整个设计采用1.8V电源电压,平均消耗电流20 mA.给出了版图及仿真结果.     

一个没有采用校准技术的12位分辨率100兆采样率的流水线模数转换器

本文给出了一个基于0.18um CMOS工艺的12bit 100MS/s的流水线ADC。其中第一级采用了3.5比特结构以降低对电容匹配的要求,采样保持放大器、第一级和第二级均采用了自举开关以改善ADC线性度,后级采用级缩减技术节省了功耗和面积。当输入信号频率为15.5MHz、采样率为100MHz时,该ADC达到了79.8dB的SFDR和10.5bit的有效位数。芯片采用1.8V电压供电,包含输出驱动的总功耗为112mW, 芯片面积为3.51mm2 。