嵌入式MPEG-2实时传输流分析系统设计

提出一种嵌入式实时MPEG-2传输流分析系统.描述了软硬件的架构,叙述了实现流程和实现过程中所需要注意的关键问题,并且和其它码流分析仪作了比较,指出该系统的优势和使用范围.     

反辐射导弹导引头中频数字接收机研究

研究了一种反辐射导弹导引头中的中频数字接收机的设计和实现方案.该接收机利用带通采样对输入的中频信号进行数字化处理.提出了一种改进的分布式算法,该算法利用查找表的方式代替乘法-累加操作并能同时实现对混频信号的滤波和抽取处理.这种方法实时性强并能有效的节约芯片逻辑,可有效的应用于反辐射导弹导引头电路设计中.     

Design of High Speed AWGN Communication Channel Emulator

This paper presents a method for designing a high accuracy white gaussian noise generator suitable for communication channel emulation. The proposed solution is based on the combined use of the Box-Muller method and the central limit theorem. The resulting architecture provides a high accuracy AWGN with a low complexity architecture for a digital implementation in FPGA. The performance is studied by means of MATLAB simulations and various complexity figures are given.     

128×128红外焦平面阵列时序分析与温控电路设计

介绍了微测辐射热计的 12 8× 12 8凝视型非致冷红外热像仪的系统框图 ,论述了一种新型的红外焦平面阵列温控电路设计方案以及读出电路时序的FPGA实现方法 .该方案具有高集成度、高精度、低成本、布线简单等优点 ,为热像仪系统的研制开发提供了设计思想 .     

数字通信系统设计中FPGA的仿真

在大规模的FPGA设计中，由于逻辑过于复杂，给仿真与调试工作带来很大难度。本文结合“实用化综合接入系统”边缘路由器子系统的设计，结合仿真软件提供的接口，提出用测试程序自动生成测试向量，自动完成仿真结果检查的方法，大大降低了仿真与调试的工作量。     

基于FPGA的图像几何矩计算实时实现

在Hatamian数字滤波器算法和改进的数字滤波器算法基础上,文中设计了累加器和累加器栅格的结构,消除了几何矩计算中乘法运算,进一步简化了加法运算量,实现了基于FPGA的几何矩计算实时实现.累加器表的仿真实验表明,该累加器表能够完成图像(256×256)几何矩的实时计算,同时该累加器表也可以用于图像质心的计算.     

单片机系统的动态加密技术

单片机系统产品的加密和解密技术永远是一个矛盾的统一体。然而 ,为了更好的保护好自己的单片机技术成果和知识产权 ,加大解密成本 ,研究新型加密技术仍是保护成果的主要手段之一。文中在讨论了传统的单片机系统加密和解密技术的基础上 ,提出一种实用而有效的动态加密技术的实现方案。     

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate two systematic approaches to low-cost, low-latency CED for symmetric encryption algorithm RC6. The proposed techniques have been validated on FPGA implementations of RC6, one of the advanced encryption standard finalists.     

基于VHDL实现单精度浮点数的加／减法运算

研究了单精度浮点数加／减法的结构及其设计方法，并在Aldec公司的Active—HDL软件环境下，采用VHDL语言进行设计，并进行了仿真验证，计算精度可以达到10^-7。     

A reconfigurable VLSI-based double-lens tracking camera

Watching and tracking an object while seeing a much wider view is one of advantages of the eye system. We proposed and developed a tracking camera system that mimics the eyes by using double-lens modules. In the system, a wide view is captured through the wide-lens module, while the target in it is tracked and magnified through the telescopic lens module. Electronic circuits for tracking control are implemented onto the reconfigurable VLSI or FPGA in order to embed the parallelism in the tracking algorithm into the hardware. A successfully developed FPGA-based prototype performs high-speed tracking at the video-rate. This work was present in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27, 2007