车辆数限制的多车型校车路径问题模型及算法研究

为适应校车路径规划中校车有多种车型且每种车型数量受限的需求,建立车辆数限制的多车型校车路径问题(HFSBRP)的数学模型,并提出一种迭代局部搜索算法进行求解。该算法借助邻域随机选择的变邻域下降搜索(VND)算法完成局部提升。局部提升过程中,首先调整车型,然后再混合使用缩减路径数和提高车辆利用率的邻域解接受策略以提高算法的寻优能力,为保证解的多样性,允许接受一定偏差范围内的邻域解。此外,为避免算法过早陷入局部最优,设计了多点交换和移动的扰动规则。基于国际基准测试案例进行模型验证和算法测试,实验结果表明了模型的正确性和算法的有效性。     

可穿戴医疗设备的安全方法研究

针对可穿戴医疗设备应用中所存在的隐私保护和安全问题,在分析了已有生物密钥和量子密钥的优缺点的基础上,给出了将两者结合并用于可穿戴医疗设备安全保护中的思路;针对可穿戴医疗设备组成的异构网络的数据安全传输问题,在分析已有的密钥预分配方案的基础上,提出将其应用于可穿戴医疗设备构成的动态、异构网络中,为解决可穿戴医疗设备数据安全传输提供理论和技术基础。     

探讨异构多数据库系统的集成技术

异构多数据库集成系统是数据库领域的研究热点和难点课题。该文首先对异构多数据库系统的集成进行设计,并进一步探讨了系统集成技术的实现,涉及到模式消解技术、查询处理技术以及事务处理技术。     

浅谈异质容器在程序设计中的应用

本文旨在运用异质容器来实现数据的存取,说明异质容器是怎样应用到实践中的,通过直观描述数据交换的过程来认识运用异质容器的简便。     

基于代理的状态监控系统设计与实现

针对传统C/S结构的监控系统弊端,本文提出了一个基于代理的状态监控系统,介绍了监控客户端、监控服务器和监控代理的模型结构,详细设计了监控代理的各部分模块,采用基于XML的异构数据集成技术对系统异构数据进行集成,该监控系统具有很强的实用性,能够对设备的状态进行实时的监控。     

基于虚拟机的异构环境下无线传感器网络网关设计

在异构环境下,无线传感器网络的网关部分可能受到的安全威胁大大增大,因此网关内出现的秘密信息可能因此泄露。为了解决这一安全威胁,本文通过使用虚拟机技术,设计了一种基于虚拟机的异构环境下的无线传感器网络网关结构。该结构运用了虚拟机技术中隔离的特性,根据各应用模块的安全特点,将其分别部署在网关中的不同虚拟机内,只有在同一虚拟机内的应用程序才能对此虚拟机内的资源进行访问。通过这种方式,可以有效的避免网关中的非可信程序或者非可信用户对网关中存储的秘密信息的访问,有效的提高了网关系统的安全。     

Improving application behavior on heterogeneous manycore systems through kernel mapping

Many-core accelerators are being more frequently deployed to improve the system processing capabilities. In such systems, application mapping must be enhanced to maximize utilization of the underlying architecture. Especially, in graphics processing units (GPUs), mapping kernels that are part of multi-kernel applications has a great impact on overall performance, since kernels may exhibit different characteristics on different CPUs and GPUs. While some kernels run faster on GPUs, others may perform better in CPUs. Thus, heterogeneous execution may yield better performance than executing the application only on a CPU or only on a GPU. In this paper, we investigate on two approaches: a novel profiling-based adaptive kernel mapping algorithm to assign each kernel of an application to the proper device, and a Mixed-Integer Programming (MIP) implementation to determine optimal mapping. We utilize profiling information for kernels on different devices and generate a map that identifies which kernel should run where in order to improve the overall performance of an application. Initial experiments show that our approach can efficiently map kernels on CPUs and GPUs, and outperforms CPU-only and GPU-only approaches.     

Design and initial performance of a high-level unstructured mesh framework on heterogeneous parallel systems

OP2 is a high-level domain specific library framework for the solution of unstructured mesh-based applications. It utilizes source-to-source translation and compilation so that a single application code written using the OP2 API can be transformed into multiple parallel implementations for execution on a range of back-end hardware platforms. In this paper we present the design and performance of OP2’s recent developments facilitating code generation and execution on distributed memory heterogeneous systems. OP2 targets the solution of numerical problems based on static unstructured meshes. We discuss the main design issues in parallelizing this class of applications. These include handling data dependencies in accessing indirectly referenced data and design considerations in generating code for execution on a cluster of multi-threaded CPUs and GPUs. Two representative CFD applications, written using the OP2 framework, are utilized to provide a contrasting benchmarking and performance analysis study on a number of heterogeneous systems including a large scale Cray XE6 system and a large GPU cluster. A range of performance metrics are benchmarked including runtime, scalability, achieved compute and bandwidth performance, runtime bottlenecks and systems energy consumption. We demonstrate that an application written once at a high-level using OP2 is easily portable across a wide range of contrasting platforms and is capable of achieving near-optimal performance without the intervention of the domain application programmer.     

Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers

Codes that have large-stride/irregular-stride (L/I) memory access patterns, e.g., sparse matrix and linked list codes, often perform poorly on mainstream clusters because of the general purpose processor (GPP) memory hierarchy. High performance reconfigurable computers (HPRC) contain both GPPs and field programmable gate arrays (FPGAs) connected via a high-speed network. In this research, simple 64-bit floating-point codes are used to illustrate the runtime performance impact of L/I memory accesses in both software-only and FPGA-augmented codes and to assess the benefits of mapping L/I-type codes onto HPRCs. The experiments documented herein reveal that large-stride software-only codes experience severe performance degradation. In contrast, large-stride FPGA-augmented codes experience minimal performance degradation. For experiments with large data sizes, the unit-stride FPGA-augmented code ran about two times slower than software. On the other hand, the large-stride FPGA-augmented code ran faster than software for all the larger data sizes. The largest showed a 17-fold runtime speedup.     

Stochastic DAG scheduling using a Monte Carlo approach

In heterogeneous computing systems, there is a need for solutions that can cope with the unavoidable uncertainty in individual task execution times, when scheduling DAGs. When such uncertainties occur, static DAG scheduling approaches may suffer, and some rescheduling may be necessary. Assuming that the uncertainty in task execution times is modelled in a stochastic manner, we may be able to use this information to improve static DAG scheduling considerably. In this paper, a novel DAG scheduling approach is proposed to solve this stochastic scheduling problem, based on a Monte Carlo method. The approach is built on the top of a classic static DAG scheduling heuristic and evaluated through extensive simulation. Empirical results show that a significant improvement of average application performance can be achieved by the proposed approach at a reasonable execution time cost.