高光谱成像用高帧频CMOS图像传感器北大核心

针对高帧频、全局曝光和光谱平坦等成像应用需求,设计了一款高光谱成像用CMOS图像传感器。其光敏元采用PN型光电二极管,读出电路采用5T像素结构。采用列读出电路以及高速多通道模拟信号并行读出的设计方案来获得低像素固定图像噪声(FPN)和非均匀性抑制。芯片采用ASMC 0.35μm三层金属两层多晶硅标准CMOS工艺流片,为了抑制光电二极管的光谱干涉效应,后续进行了光谱平坦化VAE特殊工艺,并对器件的光电性能进行了测试评估。电路测试结果符合理论设计预期,成像效果良好,像素具备积分可调和全局快门功能,最终实现的像素规模为512×256,像元尺寸为30μm×30μm,最大满阱电子为400 ke^(-),FPN小于0.2%,动态范围为72 dB,帧频为450 f/s,相邻10 nm波段范围内量子效率相差小于10%,可满足高光谱成像系统对CMOS成像器件的要求。     

Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra-Deep Submicron Digital Circuit Design

This paper presents a physics-based compact gate delay model that includes all short-channel phenomena prevalent at the ultra-deep submicron technology node of 32 nm. To simplify calculations, the proposed model is connected to a compact α-power law-based (Sakurai-Newton) model. The model has been tested on a wide range of supply voltages. The model accurately predicts nominal delays and the delays under process variations. It has been shown that at lower technology nodes, the delay is more sensitive to threshold voltage variations, specifically at the sub-threshold operating region as compared with effective channel length variations above the threshold region.     

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.     

A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (C_in) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm², i.e. 0.315 mm².     

A New Design Methodology for Time-Based Capacitance-to-Digital Converters (T-CDCs)

This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 μm CMOS technology. This T-CDC consumes 8.42 μW and achieves a maximum SNR of 45.14 dB with a conversion time of 1 μs that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv.     

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process

In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits.     

一种新的射频CMOS混频器结构

提出了一种低电压高增益CMOS下变频混频器的新结构.这个结构避免了堆叠晶体管,因此可以在低电压下工作.在LO信号的频率为1.452GHz,RF信号频率为1.45GHz的情况下,仿真结果表明:混频器的增益为15dB,ⅡP3为-4.5dBm,NF为17dB,最大瞬态功耗为9.3mW,直流功耗为9.2mW.并对该混频器的噪声特性和线性度进行了分析.     

12位300MHz电流驱动型DAC

在电路误差、电路占用芯片面积相互折中和妥协的前提下提出了一种8+4结构的电流驱动型数模转换器.采用Q2 random walk方法设计了一个新型的双中心对称的电流矩阵,确保数模转换器的线性度.分析并求出了最佳电平交叉点,设计了电平钳位锁存器对开关电平限幅,DAC动态性能得到改善.在12位分辨率下,刷新率达到300MHz以上.     

低成本CMOS阵列式高速成像系统

高速摄像是研究瞬间发生的物理和化学现象的重要手段之一.针对碰撞过程,提出了应用低成本CMOS阵列式成像传感器构建高速摄像系统.成像阵列由16个可更换的CMOS单元组成,接在主板上.为了进行同步控制,实验研究了CMOS传感器的工作时序;通过延时器,使阵列式火花源分时闪光,并在CMOS快门打开的时间段内完成.实验表明,该系统可以实现对碰撞等瞬间发生过程的拍摄,为相关研究提供基础.     

1.5GHz CMOSECL输入接口的设计与测试

对一种高速CMOS ECL输入接口进行了分析研究,该接口包含一种双镜补偿的CMOS差分放大电路,采用0.18 μm CMOS工艺研制,实现了PECL电平兼容.经测试,该接口最高工作频率达1.5 GHz.