新型的芯片间互连用CMOS/BiCMOS驱动器

从改善不同类型 IC芯片之间的电平匹配和驱动能力出发 ,设计了几例芯片间接口 (互连 )用 CMOS/Bi CMOS驱动电路 ,并提出了采用 0 .5 μm Bi CMOS工艺 ,制备所设计驱动器的技术要点和元器件参数。实验结果表明所设计驱动器既具有双极型电路快速、大电流驱动能力的特点 ,又具备 CMOS电路低压、低功耗的长处 ,因而它们特别适用于低电源电压、低功耗高速数字通信电路和信息处理系统。     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

3-D MCM封装技术及其应用

介绍了超大规模集成电路（VLSI）用的3-D MCM封装技术的最新发展，重点介绍了3-D MCM封装垂直互连工艺，分析了3-D MCM封装技术的硅效率、复杂程度、热处理、互连密度、系统功率与速度等问题，并对3-D MCM封装的应用作了简要说明。     

Promising alloys for intermediate-temperature solid oxide fuel cell interconnect application

The formation of a low Cr-volatility and electrically conductive oxide outer layer atop an inner chromia layer via thermal oxidation is highly desirable for preventing chromium evaporation from solid oxide fuel cell (SOFC) metallic interconnects at the SOFC operation temperatures. In this paper, a number of ferritic Fe–22Cr alloys with different levels of Mn and Ti as well as a Ni-based alloy Haynes 242 were cyclically oxidized in air at 800 °C for twenty 100-h cycles. No oxide scale spallation was observed during thermal cycling for any of these alloys. A mixed Mn₂O₃/TiO₂ surface layer and/or a (Mn, Cr)₃O₄ spinel outer layer atop a Cr₂O₃ inner layer was formed for the Fe–22Cr series alloys, while an NiO outer layer with a Cr₂O₃ inner layer was developed for Haynes 242 after cyclic oxidation. For the Fe–22Cr series alloys, the effects of Mn and Ti contents as well as alloy purity on the oxidation resistance and scale area specific resistance were evaluated. The performance of the ferritic alloys was compared with that of Haynes 242. The mismatch in thermal expansion coefficient between the different layers in the oxide scale was identified as a potential concern for these otherwise promising alloys.     

等离子喷涂燃料电池连接板LSM薄膜的性能研究

采用等离子喷涂法在SUS 430连接板基体上制备了LSM(La0.8 Sr0.2 MnO3)薄膜。用X射线衍射仪、扫描电镜和电子探针分别研究了喷涂前后LSM的相组成、薄膜的表面形貌和元素分布。用图像分析法计算了薄膜的孔隙率。二支点法测量了有与无LSM薄膜的SUS 430基体在130～800℃时的电导率。结果发现,薄膜与基体结合良好,薄膜孔隙细小,均匀分布,且非连通;LSM的相组成在喷涂前后保持一致;当温度<330℃时,有LSM保护膜的连接板的电导率小于无LSM薄膜的连接板的电导率;温度>330℃,结果相反。有LSM保护膜的连接板在空气中,130～800℃下,最大电导率为0.60Ω-1·cm-1。     

ULSI中的铜互连线RC延迟

随着ULSI向深亚微米特征尺寸发展，互连引线成为ULSI向更高性能发展的主要限制因素。由互连引线引起的串扰噪音及RC延迟限制了ULSI的频率性能的提高，同时考虑到电迁移和功率损耗，人们开始寻找新的互连材料；低电阻率的铜互连材料和低介电常数介质的结合可以有效地发送互连线的性能，主要讨论了互连延迟的重要性以及发送和计算延迟的方法。     

低k氟化非晶碳层间介质对芯片性能的影响

讨论了通过合理设计的工艺流程将低k氟化非晶碳材料应用到制造工艺中作为互连介质对集成电路性能的影响。基于一个互连结构简化模型计算出采用低k氟化非晶碳材料作为互连介质后RC延迟、功率耗散和线间串扰的变化情况。采用低k氟化非晶碳介质后,RC延迟和功率耗散随着互连长度的增大而减小,线间串扰也得到显著抑制。     

Improved shape evolution of copper interconnects prepared by jet-stream etching

In the preparation of copper interconnects in the conductor pattern of a printed circuit board (PCB), wet etching processes are commonly adopted for creating patterns of high-density interconnects. Currently available techniques of immersion and spray etching could lead to poorly shaped wires due to complex flow fields or the disturbing puddling effect. A modified technique of arrayed jet-stream etching was developed in this work, aiming at producing well-defined copper interconnects on a PCB in a significantly shorter time. The results were appealing in that copper interconnects of 35/140 μm (thickness/width) exhibiting etching factors of greater than 6 were obtained in 20 s, much better than the conventional ones with etching factors of 3 to 5 and etching times of at least 2 min. In addition, uniformly etched copper interconnects with less than 20 μm undercuts were observed on one etching line. One additional point to note is that no banking agents or inhibitors as commonly seen in conventional etching techniques were needed in this new processing method.