大规模生物网络马尔可夫聚类的并行化算法

马尔可夫聚类算法（MCL）是在大规模生物网络中寻找模块的一个有效方法，能够挖掘网络结构和功能影响力较大的模块。算法涉及到大规模矩阵计算，因此复杂度可达立方阶次。针对复杂度高的问题，提出了基于消息传递接口（MPI）的并行化马尔可夫聚类算法以提高算法的计算性能。首先，生物网络转化成邻接矩阵；然后，根据算法的特性，按照矩阵的规模判断并重新生成新矩阵以处理非平方倍数矩阵的计算；其次，并行计算通过按块分配的方式能够有效地实现任意规模矩阵的运算；最后，循环并行计算直至收敛，得到网络聚类结果。通过模拟网络和真实生物网络数据集的实验结果表明，与全块集体式通信（FCC）并行方法相比，平均并行效率提升了10个百分点以上，因此可以将该优化算法应用在不同类型的大规模生物网络中。     

浅谈多核心与多核心结构

分析阐述了哈里斯和埃里克森的“多核心”理论,并对“多核心”和“多核心结构”进行了分析比较,最后探讨了如何建立合理的“多核心”城市空间结构,从而为进行城市规划提供了指导作用。     

基于OMAPL138的嵌入式CNC控制器硬件平台开发

针对基于PC机和专用运功控制卡的传统数控系统的不足,以及基于ARM和DSP的多处理器在通信上的不足。提出基于多核异构的OMAPL138处理器的嵌入式处理方案,构建CNC控制器的硬件控制系统,同时利用FPGA的现场可编程特性完成控制器扩展模块设计。该设计解决了PC机所缺乏的实时性以及资源的专用性问题和多处理器通信数据丢失、易出错、难维护的缺陷,并实现了现代CNC系统所需求的高性能、模块化、柔性化以及开放性。     

一种中心型有限体积孔隙–裂隙渗流求解方法及其OpenMP并行化

为高效求解单相孔隙–裂隙渗流问题,发展一种基于任意网格的三维中心型有限体积渗流求解算法,并对其进行OpenMP并行化。该算法将压力置于单元中心处;使用串联弹簧模型在空间域离散;使用显式差分格式在时间域离散;使用动态松弛求解技术,逐个单元求解。算例研究表明,该算法与有限元相比具有类似的精度,但求解效率更高。OpenMP并行化使得该算法运算速度在CPUi7–3770上可提高至4.0倍,在CPUi7–4770上可提高至4.2倍;两台机器上的并行效率均高达50%以上。     

一种快速求解大规模安全约束最优潮流的多核并行方法

针对传统安全约束最优潮流计算方法占用内存大、计算时间长的问题,提出了一种多核并行安全约束最优潮流算法。由正常运行状态检验预想故障状态,选取少量严重故障逐步修正正常运行状态,直到所有状态都得到满足。多核并行技术用于实现算法从高到低层次的高效率整体并行,以提高计算速度。其中,采用有向无环图并行数值分解算法实现正常运行状态修正过程的细粒度并行,并根据算法特性,直接实现预想故障状态检验过程的粗粒度并行。某省-3301节点系统(预设693个故障)等3个系统的计算结果表明:随着系统规模的扩大,所提方法占用内存不足传统方法的1%,且计算速度可快于传统方法三个数量级以上。     

基于多核DSP激光成像雷达数据处理系统

采用多核DSP设计了一个用于地面目标检测的激光雷达实时图像处理系统。在详细分析算法各模块资源消耗量的基础上,完成了硬件电路设计,实现了以主辅拓扑结构为框架的软件并行处理系统开发。在系统实现时,先将图像进行分区,并合理地将分区后的图像分配到四个DSP核中进行处理。最后,将并行系统进一步扩展到双核和六核,并与单核系统进行性能比较。对算法运算时间的测试结果表明,系统处理一帧图像仅需50 ms达到了实时性要求。结果表明,对于固定负载的处理系统,单纯地通过增加并行的核数来提高加速比的幅度是有限的。当增加并行的核数已不能明显地提高计算效率时,在系统设计中应着重减少每个核串行运算的负载量。     

基于多内核兼容的国网安全浏览器关键技术研究

为解决国家电网有限公司工作人员日常工作中操作业务系统时因浏览器版本问题遇到的各种困扰,文章研究了基于多内核兼容的国网安全浏览器关键技术。通过设计研发多内核企业级浏览器,采用Chromium多进程模型,实现Chrome和IE多内核浏览。在此基础上,详细描述使用国密算法进行浏览器安全加固技术的详细做法。测试结果表明,该安全浏览器有效解决了兼容和安全问题,实现单一浏览器兼容所有业务系统,提升客户端操作体验,降低信息化系统开发和运维成本,为国家电网有限公司信息化建设发展提供扎实基础。     

Efficient automatic parallelization of a single GPU program for a multiple GPU system

Single GPU scaling is unable to keep pace with the soaring demand for high throughput computing. As such executing an application on multiple GPUs connected through an off-chip interconnect will become an attractive option to explore. However, much of the current code is written for a single GPU system. Porting such a code for execution on multiple GPUs is difficulty task. In particular, it requires programmer effort to determine how data is partitioned across multiple GPU cards and then launch the appropriate thread blocks that mostly accesses the data that is local to that card. Otherwise, cross-card data movement is an expensive operation. In this work we explore hardware support to efficiently parallelize a single GPU code for execution on multiple GPUs. In particular, our approach focuses on minimizing the number of remote memory accesses across the off-chip network without burdening the programmer to perform data partitioning and workload assignment. We propose a data-location aware thread block scheduler to schedule the thread blocks on the GPU that has most of its input data. The scheduler exploits well known observation that GPU workloads tend to launch a kernel multiple times iteratively to process large volumes of data. The memory accesses of the thread block across different iterations of a kernel launch exhibit correlated behavior. Our data location aware scheduler exploits this predictability to track memory access affinity of each thread block to a specific GPU card and stores this information to make scheduling decisions for future iterations. To further reduce the number of remote accesses we propose a hybrid mechanism that enables migrating or copying the pages between the memory of multiple GPUs based on their access behavior. Hence, most of the memory accesses are to the local GPU memory. Over an architecture consisting of two GPUs, our proposed schemes are able to improve the performance by 1.55× when compared to single GPU execution across widely used Rodinia [17], Parboil [18], and Graph [23] benchmarks.     

A few bad ideas on the way to the triumph of parallel computing

Parallelism has become mainstream, in the multicore chip, the GPU, and the internet datacenter running MapReduce. In my field, large-scale scientific computing, parallelism now reigns triumphant.     

Locality‐Conscious Nested‐Loops Parallelization

To speed up data‐intensive programs, two complementary techniques, namely nested loops parallelization and data locality optimization, should be considered. Effective parallelization techniques distribute the computation and necessary data across different processors, whereas data locality places data on the same processor. Therefore, locality and parallelization may demand different loop transformations. As such, an integrated approach that combines these two can generate much better results than each individual approach. This paper proposes a unified approach that integrates these two techniques to obtain an appropriate loop transformation. Applying this transformation results in coarse grain parallelism through exploiting the largest possible groups of outer permutable loops in addition to data locality through dependence satisfaction at inner loops. These groups can be further tiled to improve data locality through exploiting data reuse in multiple dimensions.