基于FPGA的直接序列扩频发射机的设计与实现

This paper presented an implementation of a direct sequence spread spectrum transmitter, which used FPGA as a hardware platform, and Max- plusII as a design tool. And the modules were designed using Verilog HDL and the top layer was designed based on graphical method. In this design, Bits to be transmitted are read from ROM circularly, and the channel coding utilizes (2,1,7) convolution codes. The spread spectrum module adopted kasami codes with a spread length 255. And a 3 bit quantization is used for polar transformation. Between every bit, 7 bits were inserted in interpolation module. The output filter is a 16 level FIR filter. The Verilog HDL codes, block diagram of the whole system, and the simulation results were presented in this paper. The result of the simulation showed that this is a high accurate and stable design without any glitch.     

基于FPGA的IEEE802.11协议帧生成器的设计

IEEE 802.11, the most popular standard, defines the protocols which covers all of Ethernet based wireless communication. This paper presented an implementation of IEEE 802.11 Frame Generator, which used FPGA as a hardware platform. This generator constructs the 802.11 frame and supplied it to DSSS as signal to be sent. There are 3 modules in this design. The 1st is the global control module, the 2nd module is CRC- 32 check and the 3rd is used to produce frame serial number. The characteristic of this de- sign is that the signal process and the transmission are made at the same time, i.e. real time processing. That is important to the wireless network device, which has narrower bandwidth and lower process energy. The Verilog HDL codes, block diagram of the whole system, and the simulation results were described in this paper.     

改进型安全自组网按需距离向量路由协议研究

提出了一种新的效能较高的具备安全鉴别功能的自组网按需距离向量路由协议ESAODV。该安全协议采用HORSEI认证机制，其签名和验证的计算速度比公钥算法快很多，它的安全性基于单向散列算法，且不需收发者之间的时间同步。理论分析和网络仿真结果表明，与最新因特网协议草案所提出的方案相比，安全协议ESAODV具有较好的性能和实用性。