脊髓血管畸形血管内栓塞治疗

目的探讨经血管内治疗脊髓动静脉畸形(AVM)的方法.方法本组41例脊髓AVM.3例用3个0真丝线段栓塞,14例采用干燥硬脑膜栓塞,16例采用PVA栓塞,8例采用α-氰基丙烯酸正丁酯(NBCA)胶粘合剂经微导管超选择性栓塞.结果病灶完全栓塞27例,部分栓塞14例,肢体瘫痪症状改善36例,其中5例症状未改善.平均随访32个月,有18例症状完全恢复正常,5例复发,无再出血发生.结论血管内栓塞是治疗脊髓血管畸形的有效方法.     

应用三测定子法测量直齿轮周节累积误差的实验研究

应有和三测定子法测量直齿轮的ｓ个调节误差，并结合理论分析计算，可得到相应的周节累积误差，并得出如下结论：Ｓ个周节误差和周节累积误差与齿轮轮齿表面的加工精度有关；随着周节数的增大，Ｓ个周节误差与周节累积误差的变化范围也大。三测定子法是方便可行的，且比二测定子法更为有效。     

频率量转换数字量的集成电路设计技术

传感器在各领域有着广泛应用,为了测试传感器输出的频率值,在传感器与计算机之间需要一种可以将频率量转换为数字量的专用集成电路。介绍了输出为频率量的传感器测试基本原理,设计了基于这种传感器而研制的专用集成电路,介绍了其电路功能,电路逻辑结构,电路核心器件逻辑设计及功能验证。     

Prevention from Soft Errors via Architecture Elasticity

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.     

An Elastic Architecture Adaptable to Various Application Scenarios

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status~zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.     

基于粘聚力的沥青稳定碎石设计方法研究

针对沥青稳定碎石混合料对抗拉性能的要求,采用结合混合料抗压强度及抗拉强度的粘聚力法,确定沥青稳定碎石混合料的沥青用量,将结果与传统的马氏方法进行比较,并应用两种沥青膜厚度计算方法计算了有效沥青膜厚度,得出粘聚力法使混合料获得具有更好粘聚力的沥青膜厚,且沥青膜厚范围约为6.5μm~9.0μm。     

基于iCAN总线的中波发射机监控系统

描述一种基于CAN总线的中波发射机监控系统的实现方案.该方案通过工业CAN-bus现场总线控制系统iCAN构建分布式数据采集网络,并分析了系统工作原理和软硬件结构.     

基于Harris角点和SIFT算法的车辆图像匹配

车辆图像匹配广泛应用于车辆识别和跟踪,其中SIFT(Scale Invariant Feature Transform)特征匹配算法是当前国内外特征点匹配研究的热点,但针对车辆等刚体特征明显的目标,SIFT算法在时间复杂度和稳定性方面留出了改进空间.针对车辆图像匹配,本文基于Harris角点检测对SIFT算法进行改进.实验结果表明:该方法在车辆图像匹配时,稳定性和实时性优于SIFT算法.     

An FFT Performance Model for Optimizing General-Purpose Processor Architecture

General-purpose processor (GPP) is an important platform for fast Fourier transform (FFT),due to its flexibility,reliability and practicality.FFT is a representative application intensive in both computation and memory access,optimizing the FFT performance of a GPP also benefits the performances of many other applications.To facilitate the analysis of FFT,this paper proposes a theoretical model of the FFT processing.The model gives out a tight lower bound of the runtime of FFT on a GPP,and guides the architecture optimization for GPP as well.Based on the model,two theorems on optimization of architecture parameters are deduced,which refer to the lower bounds of register number and memory bandwidth.Experimental results on different processor architectures (including Intel Core i7 and Godson-3B) validate the performance model.The above investigations were adopted in the development of Godson-3B,which is an industrial GPP.The optimization techniques deduced from our performance model improve the FFT performance by about 40%,while incurring only 0.8% additional area cost.Consequently,Godson-3B solves the 1024-point single-precision complex FFT in 0.368 μs with about 40 Watt power consumption,and has the highest performance-per-watt in complex FFT among processors as far as we know.This work could benefit optimization of other GPPs as well.