A D2D-Based Solution for MTC Connectivity Problem in NOMA-Based Cellular IoT Networks: Dynamic User Grouping and Resource Allocation

Mobile Networks and Applications - In a cellular network (CN), cellular users (CUs) located nearby machine type communications (MTC) devices (MTC-Ds) may act as uplink gateways to relay data to the...     

A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability

Conventional structure of delay locked loops (DLLs) is modified to achieve better jitter and smaller lock time. In the proposed structure, analog charge pump is eliminated, to remove the problems of leakage current on output capacitance, and is replaced by combination of a digital accumulator (ACC) and a digital-to-analog converter. A programmable ACC is also proposed, to dynamically control the loop gain and lock time. When the loop enters to lock region at the first time, a lock detector block disables ACC and equivalent digital code is stored on a latch array. So, a fixed control voltage controls delay elements and the systematic jitter, due to periodic discharge of control voltage. RMS jitter of less than 33.5 and 1.6 ps are achieved at 20 and 625 MHz operating frequencies, respectively, when the supply is subject to 110 mV random noise and also 40 mV periodic noise, related to generated clock signals. Lock time is reduced from 38 to 2 µs at 20 MHz, and also from 900 to 45 ns at 600 MHz, when the proposed dynamic control mechanism is applied on the loop. Total power consumption for the main core of DLL is 7.85 mW at 1.8 V supply in 0.18 µm CMOS process.     

Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy

The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, E_g, to absolute temperature. The previous works all consider E_g as a constant, independent of temperature variations. However, E_g varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of E_g to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, 2005), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2–92 °C. Accurate analysis on the simplified polynomial reveals that the TC of V_BE must be corrected to ?1.72 mV/°K at 27 °C which has been formerly reported about ?1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, 2001) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, 2007), ?2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, 2001), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, 2002), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, 1999), and ?2.2 mV/°K in Jones and Martin (Analog integrated circuit design, 1997), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, 1995). Another important conclusion is that the typical weighting coefficient of TC+ and TC? terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when E_g is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, 2001). Neglecting the temperature dependence of E_g might introduce a relative error of about 20.5 % in TC of V_BE. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of E_g is ignored.     

Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

The conventional single-stage comparators, as the basic elements of analogue-to-digital converters (ADCs), are modified for offset and mismatch errors to be utilised in multi-bit per stage pipeline structures. At first, in single-stage comparators, pre-amplification and latch operations are managed by temporary domination of positive or negative feedback via the bulk potential variations in PMOS (p-channel metal oxide semiconductor) devices. Then, the offset correction scheme is added to provide highly matched unit cells within the sub-ADCs of the pipeline structure. Monte-Carlo analysis with 100 iterations shows that input-referred offset reduces to 0.35 mV at σ, while input offset was randomly applied from a Gaussian distribution with 30 mV at 3σ. Using as unit cells of sub-ADCs in a 12-bit 100 MS/s pipeline ADC, ENOB (and SFDR) would be improved from 8.5-bits (and 53.6 dB) to 11.25-bits (and 74.2 dB), when offset error and bulk potential of PMOS devices experiences random variations with 25 mV and 60 mV at 3σ, respectively. Power consumption reaches to 0.45 mW at 625MS/s comparison speed. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 µm CMOS technology.