排序方式: 共有19条查询结果,搜索用时 31 毫秒
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具有片上多段基准源的14位宽温度范围高SNDR全差分逐次逼近型模数转换器 总被引:1,自引:1,他引:0
介绍了一种带有片上多段带隙基准源的14位低功耗自定时全差分逐次逼近型模数转换器。采用一个在-40到120℃温度范围内具有1.3ppm/℃温度系数的片上多段带隙基准电压源来为逐次逼近型模数转换器提供高精度基准电压源。设计中用格雷码代替二进制编码来减少衬底噪声从而增加整个系统的线性度。采用自定时位循环来增加时间利用率。该14位模数转换器利用TSMC 0.13μm CMOS工艺流片。该逐次逼近型模数转换器在室温2M/s 转换速率条件下能够获得81.2dB SNDR (有效位数13.2) 和85.2dB SFDR,并且在2M/s转换速率下在-40到120℃温度范围内能够保持12位以上有效位数。 相似文献
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DSOI-a novel structure enabling adjust circuit dynamically 总被引:1,自引:0,他引:1
A double silicon on insulator (DSOI) structure was introduced based on fully depleted SOI (FDSOI) technology. The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices. Based on DSOI ring oscillator (OSC), this paper focused on the theoretical analysis and electrical test of how the OSC''s frequency being influenced by the back gate electrodes (soi2n, soi2p). The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias. According to the different requirements of the circuit designers, the circuit performance could be improved by positive soi2n and negative soi2p, and the power consumption could be reduced by negative soi2n and positive soi2p. The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing. 相似文献
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为满足种类繁多、功能复杂集成电路的单粒子效应评估需求,克服目前国内地面单粒子辐照实验环境机时紧张、物理空间有限等方面的限制,设计实现了一款高效通用的集成电路单粒子效应测试系统。创新性地采用旋转立体垂直结构,包含一个多现场可编程门阵列(FPGA)电测试平台、运动控制分系统和被测器件装载板。便携式箱体结构仅需3个DB9接口即可完成所有与外界连线;基于LabVIEW实现上位机交互界面,界面友好;基于多FPGA平台实现下位机测试程序,灵活可扩展,通用性强。可实现8种300及以下管脚集成电路的一次安装、自动切换和10°~90°的角度辐射。实时监控并后台记录翻转数据、翻转时间、电路状态等细节信息,测试频率可达100 MHz。已通过专用集成电路(ASIC)、静态随机存取存储器(SRAM)、控制器局域网络(CAN)接口电路等集成电路的多次实测,验证了该系统的可靠性及其高效稳定、集成度高、安装调试方便等特点。 相似文献
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A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell (LC),with a multi-mode based on 3-input look-up-table(LUT),increases logic density about 12%compared to a traditional 4-input LUT.The logic block(LB),consisting of 2 LCs,can be used in two functional modes:LUT mode and distributed read access memory mode.The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource.The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming.The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly.Moreover,the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si),a dose rate survivability of 1.5×1011rad(Si)/s and a neutron fluence immunity of 1×1014 n/cm2. 相似文献
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