A Robust and Power-Effcient SoC Implementation in 65nm

Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65nm CMOS LP/GP process technology. It integrates a 1GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.     

Physical Implementation of the Eight-Core Godson-3B Microprocessor

The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers.It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units.It contains 582.6 M transistors within 300 mm2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows.In Godson-3B,advanced clock distribution mechanisms including GALS (Globally Asynchronous Locally Synchronous) and clock mesh are adopted to obtain an OCV tolerable clock network.Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication.The power reduction of Godson-3B is maintained by MLMM (Multi Level Multi Mode) clock gating and multi-threshold-voltage cells substitution schemes.The highest frequency of Godson-3B is 1.05 GHz and the peak performance is 128 GFlops (double-precision) or 256 GFlops (single-precision) with 40 W power consumption.     

发动机模拟试验台

发动机模拟试验是利用计算机,单片机联合工作,对发动机试验台进行实时仿真,具有形象,逼真,节省开支等优点。同时,具有发动机实际试验中所不可能做的故障诊断部分,更加有利于教学,培训。在实际教学中收到的很好的效果。     

采用同步分析的零延迟GRLS通信机制

全局异步局部同步(GALS)与频率调整相结合能够有效地降低动态功耗.针对频率切换以及跨时钟域传输开销会损害芯片性能的问题,提出一种基于计数器的分频方法.该方法根据计数结果生成分频后的时钟沿,并在此基础上建立了一个全局比例同步局部同步(GRLS)的通信机制.GRIS利用2个时钟的频率及相位关系实现了零延迟的跨时钟域传输,并引进同步电路分析方法来保证其正确性和健壮性；GRIS不会对原有的时钟设计做任何改变,频率切换可以在一个周期内完成,且面积功耗开销可以忽略不计.最后通过基于GRLS建立的存储系统证明了该机制的高效性.目前GRLS已经成功地应用于一款商业SoC.     

片上偏差模型下Mesh结构时钟网络性能不确定性的分析

由于多驱动及回路特征使得Mesh结构时钟网络分析较为复杂,现有的定性或定量分析方法都难以针对具体Mesh结构设计寻求到准确的时钟不确定性约束,为此提出基于Mesh结构在片波动简化模型的时钟不确定性的遗传算法求解方法.首先将众多片上偏差源转化为单级延迟概率密度分布,然后进行多级传播叠加为Mesh结构末级驱动点延迟分布,进而缩减变量数目,合理分离时钟网络中树形结构和Mesh结构.在此基础上,借助遗传算法的全局趋优搜索能力来求解Mesh结构性能不确定性问题,以得到更为合理的时序裕量估算.与传统的蒙特卡洛分析方法及定性解析分析方法相比,基于65nm工艺的仿真实验结果证明了该方法的有效性.     

Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor

The Godson-3A microprocessor is a quad-core version of the scalable Godson-3 multi-core series.It is physically implemented based on the 65 nm CMOS process.This 174 mm~2 chip consists of 425 million transistors.The maximum frequency is 1GHz with a maximum power consumption of 15 W.The main challenges of Godson-3A physical implementation include very large scale,high frequency requirement,sub-micron technology effects and aggressive time schedule.This paper describes the design methodology of the physical...     

一种基于统计特性估算串扰概率的方法

该文所提出的基于统计特性估算总线串扰概率的方法与以往基于数据流的方法相比，具有更短的运行时间，且精度相当，可以更有效地为综合工具采取相应避免措施提供参考依据。