Design and calibration of a laminar soil box suitable for a low-capacity shake table using free-field tests on Ganga sand

The present study concentrates on design, commissioning and calibration of a uniaxial laminar soil box suitable for use on a low base-shear capacity shake table available at IIT Kanpur, India. The box is designed to simulate the behavior of soil deposits subjected to earthquake motions, with minimal boundary effects due to reflection of waves at the boundary. The 1.1 m × 1.6 m × 0.765 m box is comprised of a series of individual lamina supported independently on multiple roller bearings guided through a guide channel. The outer frame connected to the guide rods is designed in such as way that it can transfer the self weight of each lamina out of the shake table. A series of free-field tests are carried out on dry Ganga sand sample to calibrate the box. Dynamic response parameters, such as acceleration, displacement, stress-strain behavior, strain-dependant modulus and damping ratio of the sand at various depth are investigated. Large strain and subsequent increased inelasticity is observed towards the top of the sand bed. The experimental results are further compared with equivalent-linear SHAKE analysis and nonlinear finite element ground response analysis of the free-field soil using OpenSees for assessing the performance of the laminar box.     

Sensitivity of Shallow Foundation Response to Model Input Parameters

From a predictive point of view, it is desirable to characterize the effect of varying model input parameters on the seismic response of soil-foundation systems. In this paper, this issue is studied for shallow foundation systems in dry dense sand with varying vertical factors of safety, embedment depths, demand levels, and moment to shear ratios. Response parameters considered are the moment, shear, sliding, settlement, and rotation demands of the foundation. First-order sensitivity analyses indicate that among the soil input parameters, the friction angle has the most significant effect on capturing the foundation force and displacement demands. Furthermore, the uncertainty in friction angle contributes 80% of the variance of the settlement demand and 40% of the variance of the moment demand. It is also found that the uncertainty in Poisson’s ratio has a marginal effect in predicting the studied foundation response. Although the findings of this study are limited to the parameter space considered herein and care should be taken for broader applicability, it does shed light on which parameters uncertainty should be minimized.     

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for super-threshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows /spl sim/2.5/spl times/ improvement in throughput at iso-power compared to a conventional design.     

Seismic response of low-rise steel moment-resisting frame (SMRF) buildings incorporating nonlinear soil-structure interaction (SSI)

Nonlinear behavior at the soil-foundation interface due to mobilization of the ultimate capacity and the associated energy dissipation, particularly in an intense earthquake event, may be utilized to reduce the force and ductility demands of a structure, provided that the potential consequences such as excessive settlement are tackled carefully. This study focuses on modeling this nonlinear soil-structure interaction behavior through a beam-on-nonlinear-Winkler-foundation (BNWF) approach. The results are compared with those from fixed-base and elastic-base models. It is observed that the force and displacement demands are reduced significantly when the foundation nonlinearity is accounted for. Moreover, the foundation compliance is also found to have a significant effect on the structural response.     

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%)     

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current

Wavelet transform has the property of resolving signal in both time and frequency unlike Fourier transform. In this work, we show that time-domain information obtained from wavelet analysis of supply current can be used to test the frequency specification of analog filters efficiently. The pole/zero locations in the frequency response of analog filters shift due to change in component values with process variations. It is essential to test the filters for the shift in frequency response and fix it during production test. Wavelet analysis of supply current can be a promising alternative to test frequency specification of analog filters, since it needs only one AC stimulus and is virtually unaffected by transistor threshold variation. Simulation results on two test circuits demonstrate that we can estimate pole/zero shift with less than 3% error using only one measurement, which requires about 18 measurements in the conventional technique.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN, USA. He has worked in the EDA industry on RTL synthesis and verification for about three years. His research interest includes design methodologies for high-performance low-power testable VLSI system, defect-based testing, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN, USA. He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).     

Device optimization for digital subthreshold logic operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.     

Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits

Scaling of silicon transistors continue in the sub 100-nm regime amidst severe roadblocks. Increased short-channel effects, rising leakage currents, severe process parameter variations are only a few of the overwhelming challenges that the device and circuit designers are faced with. In an attempt to alleviate the problems associated with the scaling of silicon transistors, researchers have began a quest for novel alternate materials in a post-Si nanoelectronics era. Of the different materials investigated so far, carbon nanotubes with their superior transport properties, excellent thermal conductivities and high current handling capacities have proved to be a potential heir to Si. This paper reviews the promise of carbon nanotube field-effect transistors as future devices for high-performance as well as low-power electronics.     

Dramatic improvements in toughness in poly(lactide-co-glycolide) nanocomposites

Poly(lactide-co-glycolide) (PLG), a biocompatible and biodegradable polymer, is dramatically toughened by adding small amounts of surface modified clay nanoparticles. The elongation during tensile tests increases from 7% for the pure polymer to 210% for the nanocomposite, accompanied with a modest increase in modulus. In contrast, PLG nanocomposites based on fumed silica treated with hexamethyldisilazane show only modest improvements in toughness. Electron microscopy, X-ray scattering, rheometry, and dielectric relaxation spectroscopy are used to investigate the toughening mechanism. Multiple crazing occurs in the clay nanocomposite after yielding. Small angle X-ray scattering studies show significant orientation of the clay nanoparticles along the tensile stress direction during deformation. The clay nanocomposites show a new, slow relaxation mode, most likely due to interfacial adsorbption of PLG chains on the surface of the clay nanoparticles. The dramatic increase in toughness is attributed to physical crosslinks introduced by the clay nanoparticles, a mechanism absent in the PLG/silica nanocomposites. The physical crosslinks increase the brittle fracture strength of the polymer and, consequently, trigger a toughening mechanism via multiple crazing and shear yielding.     

Leakage Power Analysis and Reduction for Nanoscale Circuits

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.