Gold Drugs with {Au(PPh3)}+ Moiety: Advantages and Medicinal Applications

Following the success of Auranofin as an anti-arthritic drug, search for novel gold drugs has afforded a large number of [L−Au(PPh₃)] complexes that exhibit notable salutary effects. Unlike Au(III)-containing species, these gold complexes with {Au(PPh₃)}⁺ moiety are stable in biological media and readily exchange L with S- and Se-containing enzymes or proteins. Such exchange leads to rapid reduction of microbial loads or induction of apoptotic cell death at malignant sites. In many cases the lipophilic {Au(PPh₃)}⁺ moiety delivers a desirable toxic L to the specific cellular target in addition to exhibiting its own beneficial activity. Further research and utilization of this synthon in drug design could lead to novel chemotherapeutics for treatment of drug-resistant pathogens and cancers.     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

Experimental study of paddy drying in a vortex chamber

The intensification of interfacial mass, heat, and momentum transfer makes vortex chambers potentially interesting for the efficient drying of paddy, allowing shorter drying times and/or more compact equipment. The presence of a shell introduces particular challenges. Intraparticle diffusion limitations are strong and may reduce the advantage from intensified interfacial mass and heat transfer and the efficiency of air usage. Furthermore, high shear and normal stresses in the fast rotating particle bed may cause damage to the paddy shell, posing problems for transport and storage. With these specific aspects in mind, the use of vortex chambers for paddy drying is experimentally evaluated.     

Development of an Online Heat Index Measurement System for Thermal Comfort Determination

This paper presents the development of a reliable heat index (HI) measurement system for evaluating the thermal comfort of a particular building or a particular area. The HI is an index that combines air temperature and relative humidity (RH) to determine the human-perceived equivalent temperature. To measure the air temperature and RH, temperature to digital converter and RH to voltage converter is used. HI is calculated online with the help of embedded firmware of the microcontroller. This calculated value is then transferred to the computer through standard RS 232 serial port. The same sensor node is tested with the RS 485 network standard by changing the transceiver of the node. The system is calibrated using four standard saturated binary salt solutions.     

Enhancement of properties of recycled coarse aggregate concrete using bacteria

Due to rapid construction, necessity for raw materials of concrete, especially coarse aggregate, tends to increase the danger of early exhaustion of the natural resources. An alternative source of raw materials would perhaps delay the advent of this early exhaustion. Recycled coarse aggregate (RCA) plays a great role as an alternative raw material that can replace the natural coarse aggregate (NCA) for concrete. Previous studies show that the properties of RCA concrete are inferior in quality compared to NCA concrete. This article attempts to study the improvement of properties of RCA concrete with the addition of bacteria named as Bacillus subtilis. The experimental investigation was carried out to evaluate the improvement of the compressive strength, capillary water absorption, and drying shrinkage of RCA concrete incorporating bacteria. The compressive strength of RCA concrete is found to be increased by about 20% when the cell concentration of B. subtilis is 10⁶ cells/ml. The capillary water absorption as well as drying shrinkage of RCA are reduced when bacteria is incorporated. The improvement of RCA concrete is confirmed to be due to the calcium carbonate precipitation as observed from the microstructure studies carried out on it such as EDX, SEM, and XRD.     

Time delays and angles of arrival estimation using known signals

Channel estimation in a multipath mobile communication system is addressed in this paper, and a novel approach based on the linear prediction in frequency domain and the singular value decomposition technique is presented for joint estimation of the angles of arrival and the time delays of multiple reflections of a known signal. Simulation results illustrating the performance of the proposed algorithm are included, and the results show that the proposed method is close in accuracy when compared to the iterative maximum-likelihood method. However, when the two methods are compared in computational complexity, it is demonstrated that the proposed method reduces the complexity to nearly half of that of the maximum-likelihood method. The Cramer–Rao bounds are computed for comparison.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.