A robust low quiescent current power receiver for inductive power transmission in bio implants

In this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC–DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC–DC converter has variable conversion ratios and synchronous controller that lets the DC–DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0–10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%.     

单片集成直流-直流转换器的效率提高方法

采用SMIC 0.13μm CMOS工艺,设计实现了开关频率达到250 MHz,单片集成的降压型电源转换器。为了提高电源转换效率,该转换器中的片上电感采用非对称性设计方法,提高了电感的品质因数。采用了高密度片上滤波电容来稳定输出电压,同时对单位电容尺寸的优化设计减小了电容的等效串联电阻以及输出电压纹波。测试结果表明,芯片输入电压为3.3 V,当输出2.5 V电压时,峰值效率达到了80%,最大输出电流达到270 mA;当输出1.8 V电压时,峰值效率达到了70%,最大输出电流达到400 mA。     

Design and implementation of a 0.8 V input, 84% duty cycle, variable frequency step-up converter

A 0.8 V input, 84% duty cycle, variable frequency CMOS DC-DC step-up converter with integrated power switches has been presented in this paper. The converter has the properties of both the current mode and hysteric control mode operations. The inductor charging time of the topology is designed to be inversely proportional to the input voltage and as a result the inductor current disturbance dies out immediately. Hence, no external components and extra I/O pins are required for the compensation of the current loop. The step-up converter has been fabricated with a standard pseudo BiCMOS process. Special MOS device of threshold voltage 0.5 V and start-up circuitries enable the converter to start from a voltage as low as 0.8 V. The real time data show that the converter can boost 0.8 V to as high as 5 V, which makes it suitable for low voltage applications. The efficiency of the chip has been found over 75 % for the entire load range from 10 to 100 mA.     

用于神经刺激器的单电感双极性直流电压转换器

提出了一种应用于神经电刺激器的单电感双极性输出(SIBO)的直流电压转换器,具有良好的轻载效率和较低的设计复杂度。提出的SIBO系统只使用一个电感,通过两相控制同时输出正负电压,降低了控制复杂度,减少了开关通断次数,提高了效率。同时使用数模混合电路、固定导通时间调制方式实现逻辑控制,提高了系统效率,降低了设计复杂度。SIBO系统采用单节锂电池供电,输入电压为3 V到4.2 V,输出电压在不同模式下可以分别输出 ±16 V、±12 V、±8 V、±4 V。后仿真结果表明,SIBO系统在输出电压为±16 V、负载电流为1 mA时,V_OP、V_ON的纹波分别为4.5 mV和3.4 mV;在负载电流为1.3 mA时,能够达到的最大效率为94.8%。具有效率高、纹波小、复杂度低等优势。     

Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator

A high-sensitivity voltage-to-frequency converter (VFC) using an all-MOS voltage window comparator is presented in this work. The circuit is composed of one voltage-to-current converter, one charge and discharge circuit, and one all-MOS voltage window comparator. The input voltage is converted into a current which in turn triggers the charge and discharge circuit, where a built-in capacitor is driven. The voltage window comparator monitors the variated voltage on the capacitor and generate an oscillated output of which the vibration frequency is linearly dependent to the input voltage. In this way, the worst-case linear range of the output frequency of the proposed VFC is 0-55.40 MHz verified by simulations given a 0-0.9 V input range. The physical measurement of the proposed VFC shows a 0-52.95 MHz output frequency given a 0-0.9 V input range. The error in linearity is better than 8.5% while the power dissipation is merely 0.218 mW.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

Monolithic voltage conversion in low-voltage CMOS technologies

A high-to-low switching DC-DC converter that operates at input voltages up to two times as high as the maximum voltage permitted in a low-voltage CMOS technology is proposed in this paper. The proposed circuit technique is based on a cascode bridge that maintains the steady-state voltage differences among the terminals of all of the transistors within a range imposed by a specific low-voltage CMOS technology. An efficiency of 87.8% is achieved for 3.6-0.9 V conversion assuming a 0.18 μm CMOS technology. The DC-DC converter operates at a switching frequency of 97 MHz while supplying a DC current of 250 mA to the load.     

A high-efficiency DC-DC buck converter for sub-2×VDD power supply

This paper presents a DC-DC step-down converter, which can accommodate the range of power supply voltage from VDD to sub-2×VDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the proposed design is realized by a typical 1P6M CMOS process without using any high voltage process to resolve gate-oxide reliability and leakage current problems. The core area of the proposed design is less than 0.184 mm², while the power supply range is up to 5 V. Since the internal reference voltage is 1.0 V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of battery-based power supply. Therefore, it can be integrated in a SOC (system-on-chip) to provide multiple supply voltage sources.     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

一种新的应用于开关电容DC/DC转换器的补偿电路

采用Chartered 0.35μm CMOS工艺,设计实现了输入电压范围2.7～5.5 V,负载电流高达200mA的降压式开关电容型DC/DC转换器.为了在整个输入电压和负载电流范围内稳定输出电压,并且提高输出电压精确度,在对开关电容转换器环路建模分析后,提出了一个新的应用于开关电容DC/DC转换器的频率补偿电路.该...     

用于相变存储器的超低输出纹波2X/1.5X电荷泵

本文针对相变存储器编程驱动电路,提出了一种超低输出电压纹波的开关电容型电荷泵。该电荷泵可根据输入电压的不同,自适应工作在2X/1.5X升压模式之间,以获得更高的电源转换效率。相比于传统开关电容型电荷泵,在充电阶段泵电容被充电至预先设定的电压值Vo-VDD(Vo为预期的输出电压);放电阶段,泵电容串联在输入电压VDD与输出端,通过此方法将电荷泵输出端电压稳定在Vo,并有效的降低了由于电荷分享所造成的输出纹波。在中芯国际40nm标准CMOS工艺模型下,对电路进行了仿真验证,结果表明在输入电压为1.6-2.1V,输出2.5V电压,最大负载电流为10mA,输出电压纹波低于4mV,电源效率最高可达91%。     

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7?pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200?×?280?µm². The simulation results under mixed-signal 0.18?µm 1P6M process show that this novel LDO's output voltage can recover within 1.7?µs (rising) and 2.41?µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5?V for a load current 50?mA and an output voltage of 1.8?V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100?pF. Moreover, it can achieve a PSR of ?78.5 and ?73?dB at 1 and 10?kHz, respectively.     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

Sleep-mode ready,area efficient capacitor-free low-dropout regulator with input current-differencing

This paper proposes an input current-differencing technique in designing a capacitor-free low-dropout regulator to simultaneously achieve sleep-mode efficiency and silicon real estate saving. With no minimum output current required to be stable, the regulator could greatly improve SoC efficiency during standby, which is extremely attractive for battery powered applications. Designed in TSMC 0.18-μm CMOS technology, it regulates 1.8–1.2 V supply down to 1 V with 100 mA maximum output current and can drive up to 100 pF of load parasitic capacitance. Compared with prior arts with the same sleep-mode compatibility and similar output current range, it reduces the on-chip compensation capacitance from 21 to 4.5 pF.     

A DC–DC buck converter with load-regulation improvement using dual-path-feedback techniques

A DC–DC buck converter using dual-path-feedback techniques is proposed in this paper. The proposed converter is fabricated with TSMC 0.35 μm DPQM CMOS process. The structure of the proposed buck converter includes the voltage-feedback and current-feedback design to improve load regulation and achieve high efficiency. The experimental results show the maximum power efficiency is about 94 %. The load regulation is 6.22 (ppm/mA) when the load current changes from 0 to 300 mA. With a 3.6 V input power supply, the proposed buck converter provides an adjustable power output with a voltage range is from 1 to 3 V precisely.     

单芯片高效率降压DC-DC芯片设计

介绍了一种单芯片DC-DC转换器IC设计与电路实现,其特点是宽负载电流条件下具有较高效率.芯片的设计和仿真基于上华0.6 μm双阱、混合信号CMOS工艺.芯片的工作电压范围为2～5 V,可以使用于一般的电池供电设备.对提高芯片效率的方法以及效果进行了详细的讨论分析.仿真结果表明,芯片可以产生稳定的1.8 V输出电压,并提供大于500mA的输出电流,而纹波电压却小于5 mV.芯片可以获得93.8%的最大转换效率,而且在5～500 mA的负载电流范围内,效率始终高于86.2%.     

Full On-Chip CMOS Low-Dropout Voltage Regulator

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.     

A low noise,high power efficiency supply regulator for near-field power delivery

In order to deliver near-field electromagnetic power to a biomedical device or an RFID tag efficiently, the downlink signal is preferred to be at a high voltage level. To reduce power consumption and meet low supply requirements, it is advantageous for the remote device power supply to step-down the input voltage following rectification, typically using switch-mode regulators. The output ripple of a switched capacitor converter is inversely proportional to the filtering capacitance at the output node and switching frequency. In this paper, a hybrid DC–DC converter utilizing a switched capacitor regulator in master–slave configuration with a linear regulator is presented. Linear regulator actively cancels the switching ripple, while low frequency and DC current is provided by the switched capacitor converter. The converter is designed to receive an average input voltage of 5 Vpk from the receiver coil, with an output voltage of 2 V, and 5 mA of output current. The proposed regulator is fabricated in 0.35 μm technology. The power efficiency is measured to be 67%, with a nominal peak to peak ripple of less than 2 mV at the output.     

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90?nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3???V/mA with a 1.2?V input and 1?V output. For a 100?mA load current step with the rise/fall time of 100?ps, the LDO achieves maximum output voltage drop and overshoot of less than 95?mV when loaded by a 600?pF decoupling capacitor and consumes an average bias current of 408???A. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005?mm². Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.     

Fully on-chip switched capacitor NMOS low dropout voltage regulator

This paper presents a 1.5 V 50 mA low dropout voltage (LDO) regulator using an NMOS transistor as the output pass element. Continuous time operation of the LDO is achieved using a new switched floating capacitor scheme that raises the gate voltage of the pass element. The regulator has a 0.2 V dropout at a 50 mA load and is stable for a wide load current range with loading capacitances up to 50 pF. The output variation when a full load step is applied is 300 mV and the recovery time is below 0.3 μs. It is designed in a 0.13 μm CMOS process with an area of 0.008 mm² and its operation does not require any external component.