802.11b收发系统中的全集成低功耗发送机设计

基于SMIC 0.18μm CMOS工艺,设计了一个应用于IEEE 802.11b收发系统的全集成低功耗发送机. 直接转换发送机包括两个Chebyshev I型低通滤波器,两个可编程增益放大器(PGA),一个单边带混频器和一个功率预放大器. 发送机以3dB为步长提供32dB增益,其最大输出功耗为-3.4dBm, EVM为6.8%. 工作在1.8V电源电压,发送机的功耗仅57.6mW. 发送机芯片面积为1.6mm×1.6mm.     

802.11b收发系统中的全集成低功耗发送机设计

基于SMIC 0.18μm CMOS工艺,设计了一个应用于IEEE 802.11b收发系统的全集成低功耗发送机.直接转换发送机包括两个Chebyshev Ⅰ型低通滤波器,两个可编程增益放大器(PGA),一个单边带混频器和一个功率预放大器.发送机以3dB为步长提供32dB增益,其最大输出功耗为-3.4dBm,EVM为6.8%.工作在1.8V电源电压,发送机的功耗仅57.6mW.发送机芯片面积为1.6mm×1.6mm.     

低功耗输出脉冲幅度和频谱可调的超宽带发送机设计

A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 × 1.4 mm^2.     

一种用于欠采样脉冲式超宽带接收机中的高速采样器

本文提出了一种用于欠采样脉冲式超宽带接收机中的高速采样器。该采样器采用时间交错拓扑结构,包含独立的采样保持电路、全定制时钟产生器和失调消除比较器三个主要模块。这三个模块在文中进行了具体的讨论和分析。该电路采用0.13um CMOS工艺制造。测试结果表明,采样器实现了最高3 GHz的采样速度。在1.2 V电源电压下,其功耗为27 mW。包含引脚的芯片总面积为1.4×0.97 mm2。     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop(PLL) is implemented in 0.13μm CMOS technology.A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump.Dynamic mismatch of charge pump is considered.By balancing the switch signals of the charge pump,a good dynamic matching characteristic is achieved.A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance.The 4224 MHz PLL achieves...     

一个用0.13um CMOS工艺实现的4224兆赫兹低抖动的锁相环

本文利用0.13um CMOS工艺实现了一个工作频率为4224兆赫兹的锁相环。 通过采用动态鉴频鉴相器缩短延时复位脉冲来最小化电荷泵引入的噪声。文中分析了电荷泵的动态失配问题。通过平衡开关信号的负载,电荷泵实现了好的动态匹配特性。本文还设计了输入端负载平衡的高速的分频器来提高锁相环的带内噪声性能。该4224MHz锁相环在10 kHz以及 1 MHz频偏处的相位噪声分别为 -94 dBc/Hz 和 -114.4 dBc/Hz。时钟抖动的均方根值为0.57ps(从100Hz到100MHz范围积分)并且使用二阶低通滤波器的参考频率杂散为 -63 dB。     

应用于802.11b无线局域网的单芯片低功耗CMOS收发机

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta （∑△） fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2.     

一种适用于“模一”多带OFDM超宽带系统中跳频产生的3.96GHz锁相环

A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.     

一种适用于多带OFDM超宽带系统中的快速跳频3子带CMOS频率综合器

A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 ×1.8 mm^2.