A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

A dual-mode analog baseband with digital-assisted DC-offset calibration(DCOC) for WCDMA/GSM receiver is presented.A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only.This method has no bandwidth sacrifice.After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm.The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz.Total baseband gain can be programmed from 6 to 54 dB.The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm~2.     

采用数字辅助直流失调消除技术适用于WCDMA/GSM接收机的双模模拟基带

A dual-mode analog baseband with digital-assisted DC-offset calibration (DCOC) for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP₂ is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13 μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm².     

一种自校准的14-bit 100-MSPs 电流舵型DAC

本论文介绍了一种14-bit, 100MS/s CMOS数模转化器的设计与实现。引入了以模拟电流校准概念为基础模拟后台自校准技术。设计采用了恒定时钟负载开关驱动电路、校准周期随机化电路和输出自归零技术来提高DAC的动态性能。芯片利用中芯国际0.13-μm CMOS工艺实现,有效面积为1.33mm×0.97mm。数字和模拟电路分别在1.2/3.3V供电下工作,总的电流消耗为50mA。测试到的微分非线性和积分非线性分别为3.1LSB和4.3LSB。在100MHz采样频率,1MHz输入信号的工作条件下,测试得到的SFDR为72.8dB。