Invisible emotion magnification algorithm (IEMA) for real-time micro-expression recognition with graph-based features

Multimedia Tools and Applications - The interest in real-time micro-expression recognition has increased with the current trend in human-computer interaction applications. Presently, there are...     

Faceless identification based on temporal strips

This paper first presents a novel approach for modelling facial features, Local Directional Texture (LDT), which exploits the unique directional information in image textures for the problem of face recognition. A variant of LDT with privacy-preserving temporal strips (TS) is then considered to achieve faceless recognition with a higher degree of privacy while maintaining high accuracy. The TS uses two strips of pixel blocks from the temporal planes, XT and YT, for face recognition. By removing the reliance on spatial context (i.e., XY plane) for this task, the proposed method withholds facial appearance information from public view, where only one-dimensional temporal information that varies across time are extracted for recognition. Thus, privacy is assured, yet without impeding the facial recognition task which is vital for many security applications such as street surveillance and perimeter access control. To validate the reliability of the proposed method, experiments were carried out using the Honda/UCSD, CK+, CAS(ME)² and CASME II databases. The proposed method achieved a recognition rate of 98.26% in the standard video-based face recognition database, Honda/UCSD. It also offers a 81.92% reduction in the dimension length required for storing the extracted features, in contrast to the conventional LBP-TOP.

     

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera’s C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.