FUZZY REPLACEMENT ALGORITHM FOR CACHE MEMORY

This paper reports a replacement procedure for cache memories. The procedure is essentially a fuzzy algorithm that makes use of 18 rules to select the cache block to be replaced. These rules are primarily a function of three parameters: age and the frequency of usage of a cache block, and the global hit ratio of the cache system. Computationally, the proposed algorithm calculates a replacement index for each cache block and the block with highest replacement index is selected as a victim. The performance of this fuzzy procedure is compared with traditional replacement algorithms such as least recently used (LRU) and first in First out (FIFO). Our simulation experiments indicate that the proposed algorithm is a strong contender to the traditional counterparts. The unique feature of the proposed algorithm is its flexibility; that is, one can always improve its performance further by fine-tuning the rules.     

Multiple overcurrent relays using a single microprocessor

The implementation of a four-overcurrent-relay system using a single 8085 microprocessor is described. The implementation is based on the concept of multitasking in microprocessors. The relays are considered to be independent of each other. Each relay is realized by a separable counter and a look-up table in the memory. The software development and hardware testing are done using the HP-64000 UX Microprocessor Development System. The system does not depend on the 8085 microprocessor; other microprocessors can be used. The hardware and software are modular, and more relays can be added     

Interrupt-driven microprocessor-based overcurrent relay

An interrupt-driven overcurrent relay for power systems using the 8085 microprocessor is presented. The relay requests processing time from the microprocessor only when a fault occurs. In this way, the microprocessor is given the opportunity to run other tasks such as diagnostic tests online during normal conditions     

A fuzzy partitioning system

Our system uses fuzzy logic to bipartition cells in VLSI circuits. The system uses fuzzy logic principles to generate net and cell indices and a bottom-up clustering algorithm to produce the two-way partition. We tested our algorithm on eleven ISCAS89 benchmark circuits and compare its performance with that of other implementations. The journal issue contains a concise summary of this article. The complete article is linked to Micro's home page on the World Wide Web (http://www.computer.org/pubs/micro/micro.htm)     

TMR neural simulation

A computer program is written to simulate the neural network realizing the discrete-time Markov model of the TMR system. The results obtained, highlighted in this paper, support the theory of the new approach to reliability and fault-tolerance analysis using neural networks.     

Multi-function protective relay on FPGA

Protective relays play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. The design and implementation of a multi-function digital protective relay on a single field programmable gate array (FPGA) is discussed in this paper. The multi-function relay monitors the frequency and the voltage of the system. An output trip signal is set whenever the voltage value or the frequency value is outside pre-determined ranges. In addition, the multi-function relay estimates the rate of the frequency change. The FPGA (Xilinx 3030PC84-100) was used in the implementation.     

Neural network realization of Markov reliability and fault-tolerance models

A feed-forward recursive neural network consisting of 2n neurons forming 2 layers, n neurons in each layer, is set to represent a discrete-time n-state Markov model of a fault-tolerant hardware. A quadratic energy function for the neural net is presented and the appropriate update equations for the weights are derived using the least mean square gradient-descent technique.     

Neural network for the reliability analysis of simplex systems

A new approach to the reliability analysis, based on neural networks, is introduced in this paper. The reliability analysis of a simple nonredundant digital system, Simplex System, with repair is used to illustrate the neural network approach. The discrete-time Markov model of simplex systems is realized using feed-forward recursive neural network. The energy function and update equations for the weights of the neural network are estabilished such that the network converges to the desired reliability of the simplex system under design. The failure rate and repair rate, satisfying the desired reliability, are extracted from the neural weights at convergence. The obtained results are verified by the conventional approach.     

Design of reconfigurable fault-tolerant VLSI/WSI processor array structures

This paper presents a new reconfiguration technique for VLSI/WSI processor arrays. The fault-tolerant capabilities of both interstitial redundancy and time redundancy are combined to provide optimal reconfiguration. Results obtained through Monte Carlo simulations show that with the proposed reconfiguration technique, a very high yield and chip area utilization is achieved. It is also shown that in the presence of harsh environments, where a high rate of transient faults occur, the proposed algorithm is more robust compared to the existing approaches.