Self-reconfiguring interconnection network for a fault-tolerantmesh-connected array of processors

An interconnection network capable of spontaneously reconfiguring a mesh-connected processor array on detection of faulty processors is presented. Although the reconfiguration process is global in nature, the network control circuitry is localised around each processor and is therefore completely modular. In addition, the structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors     

Testing systems on a chip

Developments in fault-finding circuits built into ICs which will disclose defects in today's and tomorrow's block-based designs are examined     

Telemetric estimation of the descending colon pressure changes on dogs before and after total and selective vagotomy

This experimental study describes the pressure changes of the descending colon before and after total and selective vagotomy combined with Finney's pyloroplasty as estimated by telemetry. The results obtained from the study of 20 dogs show that the motility of the descending colon is extremely reduced after total vagotomy with no change after selective vagotomy.     

Achieving at-speed structural test

In addition to structural test, BIST offers an alternative low-cost approach to at-speed testing. How should BIST be implemented to address at-speed testing? What issues remain to be solved? How can we deal with multicycle paths and different frequency domains? The author describes BIST implementation techniques to answer these questions.     

Hepatic Senescence Accompanies the Development of NAFLD in Non-Aged Mice Independently of Obesity

Senescence is considered to be a cardinal player in several chronic inflammatory and metabolic pathologies. The two dominant mechanisms of senescence include replicative senescence, predominantly depending on age-induced telomere shortening, and stress-induced senescence, triggered by external or intracellular harmful stimuli. Recent data indicate that hepatocyte senescence is involved in the development of nonalcoholic fatty liver disease (NAFLD). However, previous studies have mainly focused on age-related senescence during NAFLD, in the presence or absence of obesity, while information about whether the phenomenon is characterized by replicative or stress-induced senescence, especially in non-aged organisms, is scarce. Herein, we subjected young mice to two different diet-induced NAFLD models which differed in the presence of obesity. In both models, liver fat accumulation and increased hepatic mRNA expression of steatosis-related genes were accompanied by hepatic senescence, indicated by the increased expression of senescence-associated genes and the presence of a robust hybrid histo-/immunochemical senescence-specific staining in the liver. Surprisingly, telomere length and global DNA methylation did not differ between the steatotic and the control livers, while malondialdehyde, a marker of oxidative stress, was upregulated in the mouse NAFLD livers. These findings suggest that senescence accompanies NAFLD emergence, even in non-aged organisms, and highlight the role of stress-induced senescence during steatosis development independently of obesity.     

Design of a self-reconfiguring interconnection network forfault-tolerant VLSI processor arrays

An interconnection network capable of spontaneously reconfiguring a VLSI processor array on detection of faulty processors is presented. Although the reconfiguration process is global, the network control circuitry is localized around each processor and is therefore completely modular. The structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors. The network performance in yield enhancement is analyzed through Monte Carlo simulation. The network effectiveness in using surviving processors is close to that of an ideal network (one capable of tolerating as many faulty processors per row as there are spare processors per row). Strategies involved in testing the fault-tolerant array are also presented. Test circuitry is placed around each of the processors to enable testing of all the processors in parallel. The same circuitry is used to test the interconnection network efficiently. The additional silicon area requirements due to the network and the test circuitries are examined through the design of a prototype fault-tolerant array