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1.
The cellular neural network (CNN) paradigm is a powerful framework for analogue non-linear processing arrays placed on a regular grid. In this paper we extend the current repertoire of CNN cloning template elements (atoms) by introducing additional non-linear and delay-type characteristics. In addition, architectures with non-uniform processors and neighbourhoods (grid sizes) are introduced. With this generalization, several well-known and powerful analogue array-computing structures can be interpreted as special cases of the CNN. Moreover, we show that the CNN with these generalized cloning templates has a general programmable circuit structure (a prototype machine) with analogue macros and algorithms. the relations with the cellular automaton (CA) and the systolic array (SA) are analysed. Finally, some robust stability results and the state space structure of the dynamics are presented.  相似文献   
2.
Roska  T. 《Electronics letters》2007,43(8):427-429
Cellular wave computer architecture as a spatial-temporal universal machine on flows reflects (i) the prophecies of Turing and von Neumann, (ii) physical constraints of nano-scale technology, (iii) typical constructs in neural organisation and mechanisms, and (iv) provides for a new way of algorithmic and hardware-software framework, already implemented in some new products, including visual microprocessors. A few aspects of this new kind of computer and computing are highlighted, including the `function in layout' principle, the biological relevance in retinal modelling, and the new type of spatial-temporal algorithmic thinking beyond Boolean logic  相似文献   
3.
According to action-control theory, volition plays a mediating role between the intention to learn (motivation) and goal-directed behavior (the use of learning strategies). Although extensive theoretical work has been done to document this flow of events, more empirical studies have been needed to identify the specific means by which volitional control protects the intention to learn and maintains the attempts to learn; our intention here was to address this gap in the literature. Using data from a sample of 487 college students in two different domains, we found that the positive effects of intrinsic goal orientation and self-efficacy on cognitive engagement were augmented by volitional control. We also found that the effects of volition differed by domain as well as by the type of learning strategy being considered. These results suggest that volitional control merits greater attention from those doing research in self-regulated learning. Copyright 1998 Academic Press.  相似文献   
4.
A high speed target detection and tracking algorithm for a CNN‐UM chip is presented in this paper. The target confidence value is computed based on the fusion of target existence probabilities of features using products of weighted sums. The target decision is done with such a confidence value and target initiation is done through the temporal accumulation of the confidence. The probability of the target existence for each feature is created in the region of influence depending on the reliability and the strength of the feature. By virtue of the analogic parallel processing structure of the CNN‐UM (Roska T, Chua LO. The CNN universal machine: an analogic array computer. IEEE Trans. Circuits Systems II 1993; CAS‐40 : 163–173), real time tracking can be achieved with presently available technologies with the speed of several kilo‐frames per second. Due to the utilization of multiple features of target, robust target detection is possible via the proposed algorithm. On‐chip experiments of the proposed target‐tracking algorithm have been done and properties of the proposed approach are disclosed through the various experiments. Copyright © 2003 John Wiley & Sons, Ltd.  相似文献   
5.
A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.  相似文献   
6.
Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided medical diagnosis, or telesurgery require an enormous computing power-in the order of trillions of operations per second (TeraOPS). Compared with conventional digital technology, cellular neural/nonlinear network (CNN)-based computing is capable of realizing these TeraOPS-range image processing tasks in a cost-effective implementation. To exploit the computing power of the CNN Universal Machine (CNN-UM), the CNN chipset architecture has been developed-a mixed-signal hardware platform for CNN-based image processing. One of the nonstandard components of the chipset is the cache memory of the analog array processor, the analog random access memory (ARAM). This paper reports on an ARAM chip that has been designed and fabricated in a 0.5-μm CMOS technology. This chip consists of a fully addressable array of 32×256 analog memory registers and has a packing density of 637 analog-memory-cells/mm2. Random and nondestructive access of the memory contents is available. Bottom-plate sampling techniques have been employed to eliminate harmonic distortion introduced by signal-dependent feedthrough. Signal coupling and interaction have been minimized by proper layout measures, including the use of protection rings and separate power supplies for the analog and the digital circuitry. This prototype features an equivalent resolution of up to 7 bits-measured by comparing the reconstructed waveform with the original input signal. Measured access times for writing/reading to/from the memory registers are of 200 ns. I/O rates via the l6-line-wide I/O bus exceed 10 Msamples/s. Storage time at room temperature is in the 80 to 100 ms range, without accuracy loss  相似文献   
7.
In this paper we have developed a neuromorphic model of bottom‐up (BU) visual attentional selection. The output of a recently developed neuromorphic multi‐channel retina model has represented the input of our model. As a first step, a saliency map has been calculated for each retinal channel which, next, has been integrated into a master saliency map. Model parameters have been optimized based on human eye movement data measured during viewing dynamic natural scenes. We have tested two different strategies for weighting the channel‐specific saliency maps during integration into a master map. In the first case, channel weights have been kept constant throughout the verification measurements, whereas, in the other case, they have been updated on each frame, according to the specific properties of the visual input. Surprisingly, the constant channel weighting strategies have performed better than the continually updated ones. We have measured the model's accuracy by defining the hit ratio (concurrence) between the first few predicted locations (the most salient locations) and the measured fixation locations. Constant weighting methods have achieved ~74% hit ratio on four predictions. For a comparison, the accidental chance for this case has been less than 20%. This pure BU approach has performed surprisingly well on dynamic natural input. Some practical applications have already been made with task‐dependent simplifications. Copyright © 2008 John Wiley & Sons, Ltd.  相似文献   
8.
Below 100 nm a new scenario is emerging in VLSI design: floorplanning and function are inherently interrelated. Using mainly local connectivity, wire delay and crosstalk problems are eliminated. A new design methodology is proposed, called function‐in‐layout, that possesses: regular layout, mainly local connectivity, functional ‘parasitics’. A bio‐inspired demonstration is presented, a hyperacuity chip, with 30 ps time difference detection using 0.35 mm complementary metal‐oxide semiconductor (CMOS) technology. Copyright © 2006 John Wiley & Sons, Ltd.  相似文献   
9.
In this paper a nonlinear wave metric is introduced for object classification. It is shown that the choice of a metric is a nontrivial problem since it is easy to give examples when well-known distance measures, such as Hamming, Hausdorff, and Nonlinear Hausdorff metrics are completely inadequate for this classification. As an alternative a generalized theorem is proposed that includes the previous metrics as special cases. It is based on nonlinear wave propagation and defines a computational framework that is well-suited for parallel array processors. In this study we investigate different Cellular Neural Network (CNN) architectures and solutions for the proposed metric and analyze its VLSI implementation complexity.  相似文献   
10.
Single-layer, continuous-time cellular neural/nonlinear networks (CNN) are considered with linear templates. The networks are programmed by the template-parameters. A fundamental question in template training or adaptation is the gradient computation or approximation of the error as a function of the template parameters. Exact equations are developed for computing the gradients. These equations are similar to the CNN network equations, i.e. they have the same neighborhood and connectivity as the original CNN network. It is shown that a CNN network, with a modified output function, can compute the gradients. Thus, fast on-line gradient computation is possible via the CNN Universal Machine, which allows on-line adaptation and training. The method for computing the gradient on-chip is investigated and demonstrated.  相似文献   
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