<Emphasis Type="Italic">New-Age</Emphasis>: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components

Degradation of device parameters over the lifetime of a system is emerging as a significant threat to system reliability. Among the aging mechanisms, wearout resulting from Negative Bias Temperature Instability (NBTI) is of particular concern in deep submicron technology generations. While there has been significant effort at the device and circuit level to model and characterize the impact of NBTI, the analysis of NBTI’s impact at the architectural level is still at its infancy. To facilitate architectural level aging analysis, a tool capable of evaluating NBTI vulnerabilities early in the design cycle has been developed that evaluates timing degradation due to NBTI. The tool includes workload-based temperature and performance degradation analysis across a variety of technologies and operating conditions, revealing a complex interplay between factors influencing NBTI timing degradation.     

NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity

Recent experimental studies reveal that FinFET devices commercialized in recent years tend to suffer from more severe NBTI degradation compared to planar transistors, necessitating effective techniques on processors built with FinFET for endurable operations. We propose to address this problem by exploiting the device heterogeneity and leveraging the slower NBTI aging rate manifested on the planar devices. We focus on modern graphics processing units in this study due to their wide usage in the current community. We validate the effectiveness of the technique by applying it to the warp scheduler and L2 cache, and demonstrate that NBTI degradation is considerably alleviated with slight performance overhead.     

Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

Going vertical as in 3-D IC design, reduces the distance between vertical active silicon dies, allowing more dies to be placed closer to each other. However, putting 2-D IC into three-dimensional structure leads to thermal accumulation due to closer proximity of active silicon layers. Also the top die experiences a longer heat dissipation path. All these contribute to higher and non-uniform temperature variations in 3-D IC; higher temperature exacerbates negative bias temperature instability (NBTI). NBTI degrades CMOS transistor parameters such as delay, drain current and threshold voltage. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security. We demonstrated that a hardware intruder could leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. In this paper we provide a detailed analysis on how tiers of 3-D ICs can be subject to exacerbated NBTI. We proposed to embed threshold voltage extractor circuit in conjunction with a novel NBTI-mitigation scheme as a countermeasure against such anticipated Trojans. We validated through post-layout and Monty Carlo simulations using 45 nm technology that our proposed solution against NBTI effects can compensate the NBTI-effects in the 3-D ICs. With the area overhead of 7% implemented in Mod-3 counter, our proposed solution can completely tolerate NBTI-induced degraded threshold voltage shift of up to 60%.     

NBTI效应及其对集成电路设计的影响

可靠性设计是现代集成电路设计需要考虑的一个重要问题.对影响电路可靠性的一个最主要效应——P-MOSFET的NBTI效应进行了系统的介绍.给出了不同电压、温度下器件性能随时间变化趋势的最新研究成果.最后介绍了SPICE考虑器件器件退化的电路模拟流程.在器件尺寸日益缩小的今天,这些将成为集成电路设计关注的焦点.     

Improvement in the negative bias temperature stability of ZnO based thin film transistors by Hf and Sn doping

We assessed the performance of ZnO TFTs using Si₃N₄ gate dielectrics after various treatments. A remarkable improvement in the transfer characteristics was obtained for the O₂ plasma treated ZnO TFT and SiO₂ interlayer deposited ZnO TFT. Also, we developed amorphous hafnium-zinc-tin oxide (HZTO) thin film transistors (TFTs) and investigated the influence of hafnium (Hf) doping on the electrical characteristics of the hafnium-zinc oxide (HZO) thin film transistors. Doping with Hf can decrease the carrier concentration, which may result from a decrease of the field effect mobility, and reduce oxygen vacancy related defects in the interfacial layer. Adding tin (Sn) can suppress the growth of a crystalline phase in the HZTO films. The HZTO TFTs exhibited good electrical properties with a field effect mobility of 14.33 cm²/Vs, a subthreshold swing of 0.97 V/decade, and a high I_ON/OFF ratio of over 10⁹.     

NBTI和HCI混合效应对PMOSFET特性退化的影响

随着器件尺寸向超深亚微米的不断发展，负偏置温度不稳定性和热载流子注入对器件可靠性的影响越来越严重．研究了负偏置温度不稳定性和热载流子注入共同作用下的PMOSFET的退化问题．首先研究了高温沟道热载流子应力模式下负偏置温度不稳定性与热载流子注入两种效应对器件阈值电压和跨导漂移的影响，这两种效应的共同作用表现为一种负偏置温度不稳定性效应增强的热载流子注入效应；然后给出了这种混合效应的解释．最后提出了一种分解负偏置温度不稳定性和热载流子注入这两种效应的方法．     

超深亚微米P+栅PMOSFET中NBTI效应及其机理研究

本文深入研究了P⁺栅PMOSFET中的NBTI效应,首先通过实验分析了NBTI应力后器件特性及典型参数的退化,基于这些实验结果提出了一种可能的NBTI效应发生机制:即由水分子参与的Si-SiO₂界面处的电化学反应.最后从工艺的角度给出了减小和抑制NBTI效应的方法.     

Design of improved‐reliability nanocircuits with mixed NBTI‐ and HCI‐aware gate‐sizing formulation

Negative bias temperature instability (NBTI) and hot carrier injection (HCI) are two important processes of reliability concern in nano‐scale integrated circuits. A circuit‐level design technique to combat NBTI degradation is gate oversizing. This paper presents a new technique based on PMOS and NMOS resistance variation for the NBTI‐ and HCI‐aware gate‐sizing problem for the first time. In this technique, the area of the circuit is minimized with constraints on degraded delay due to NBTI and HCI and the transitor size. Expreimental results for several gates and ISCAS'85 benchmark circuits show that this technique imposes an area overhead of less than 1% with respect to baseline design in most cases. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

With the rapid growth of computational intelligence techniques, automatic age estimation has achieved efficiency and accuracy that benefited IC aging-mitigation applications. This paper proposes an adaptive anti-aging system scheme that uses an intelligent algorithm to monitor the frequency degradation of digital circuits. An on-chip reliability sensor with voltage controlled oscillator (VCO) architecture achieved the circuit's aging rate, featuring real-time monitoring and tolerance against PVT variations. Cuckoo intelligence-based algorithm with global search strategy could obtain the accuracy data, reduce the number of iterations, and improve use self-adjust efficiency. The loop circuit can be quickly corrected by precise voltage compensation to alleviate performance degradation. The test chip was fabricated in the TSMC 65-nm CMOS technology with a core area of 0.97 mm². The measurement results show that the resolution is 0.004% at 1.2 V and 27 °C and a self-adjust time (SAT) reaches about 1.8 μs with an operating frequency of 500 MHz, recovering at 10% aging-related degradation. In comparison with other related literatures, the resolution of the proposed method is improved by more than 2.5 times.