Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

Sophisticated on-chip interconnects using packet and circuit switching techniques were recently proposed as a solution to non-scalable shared-bus schemes currently used in Systems-on-Chip (SoCs) implementation. Different interconnect architectures have been studied and adapted for SoCs to achieve high throughput, low latency and energy consumption, and efficient silicon area. Recently, a new on-chip interconnect architecture by adapting the WK-recursive network topology structure has been introduced for SoCs. This paper analyses and compares the energy consumption and the area requirements of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, Fat-Tree and Butterfly Fat-Tree. We investigated the effects of load and traffic models and the obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements. In these results, WK-recursive interconnect generally has a higher energy consumption and silicon area requirements in heavy traffic load.     

基于标准CMOS工艺太阳能电池的微电源管理系统

文章基于CMOS太阳能电池设计了一款微电源管理系统。此电源管理系统适用于传感器网络节点和半有源电子标签之类的需要周期性短时间供电的电路。电源管理系统中包含一个电荷泵,一个片外储能电容,控制电路和一个线性稳压器。控制电路采用一种全新的结构,静态功耗基本为零。采用UMC 0.18μm CMOS工艺,当输出电流为30uA,储能电容为1uF时,一个周期可达到大于20ms的供电时间,输出电压1.8V,电源管理系统的静态电流小于1.5uA。     

Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks

Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve system utilization. This paper introduces Globally-Synchronized Frames (GSF), a framework for providing guaranteed QoS in on-chip networks in terms of minimum bandwidth and maximum delay bound. The GSF framework can be easily integrated in a conventional virtual channel (VC) router without significantly increasing the hardware complexity. We exploit a fast on-chip barrier network to efficiently implement GSF. Performance guarantees are verified by analysis and simulation. According to our simulations, all concurrent flows receive their guaranteed minimum share of bandwidth in compliance with a given bandwidth allocation. The average throughput degradation of GSF on an 8×8 mesh network is within 10% compared to the conventional best-effort VC router.     

一种组合并联大功率DC/DC变换器研究

为了全功率范围内实现ZVS、进一步扩大单机容量和各能源的组合应用,提出了一种组合并联大功率DC/DC变换器。首先给出了电路拓扑结构,分析了变换器工作原理、软开关的实现条件以及辅助电感的工作过程,提出了关键参数的设计。最后通过实验验证了理论分析的正确性。该变换器能够通过辅助网络实现各开关管在全功率范围内的ZVS,并且辅助回路可以实现开关管ZVS所需能量的调节。     

5．8GHz／0．18μm低噪声放大器噪声分析

为了优化设计的5．8 GHz低噪声放大器(LNA)后仿真的各项性能指标,分析了LNA各部分寄生效应对整个电路噪声系数和增益的影响,提出了电路设计和版图设计中应采取的各种措施,使优化后的后仿真结果与前仿真结果基本一致．在考虑MOS管栅电阻和栅感应噪声电流的情况下,后仿真噪声系数为1．6 dB,前向增益为13．7 dB,功耗为8．3 mW,达到了802．11a系统集成的要求．最后给出了LNA版图和后仿真结果．     

射频CMOS平面螺旋电感2-π等效电路模型参数的提取

从有理分式拟合方法出发,提出了用于射频CMOS平面螺旋电感2-π等效电路模型参数提取的新方法.通过比较提参后等效电路给出的S参数和实验测量的S参数,证明该方法的精度很高.此外,提参的策略非常直接,因此容易在CAD里面编程实现.提参得到的等效电路模型对于射频电路设计者来说也是非常有用的.     

高频电感器线圈损耗分析与交错气隙布置

通过对高频电感器线圈损耗的详细分析 ,发现电感器的旁路磁通会在线圈上引起额外损耗。在此基础上 ,提出一种新型气隙设计方案与铁心结构。在该结构下 ,铁心的气隙沿铁心柱交错布置 ,减少了穿越线圈窗口的旁路磁通。与通常的EE、EI型铁心电感器相比 ,它有效降低了线圈损耗。采用有限元分析软件对这种新型气隙设计方案进行了分析与验证     

AHB-PCI桥的设计及其验证方法

本文首先简要介绍了AMBA总线和PCI总线的协议特点，并在此基础上详述了AHB-PCI桥的功能及其设计思路，文章最后是关于AHB—PCI桥的一种验证方案。本设计采用TSMC0．25μmCMOS工艺进行逻辑综合，总电路规模约为35230门。目前本设计已嵌入到SoC设计中并通过了FPGA原型验证。     

一种应用于双向DC/DC变换器的新型耦合电感的设计

本文提出的"I王I"形耦合电感器通过增加磁路气隙的数量,使磁路的磁压分布更加均匀,与传统铁心电感器相比显著减小了磁路的电磁损耗、电磁干扰和线圈的涡流损耗,且增大了窗口面积。通过分析耦合电感器的磁通分布,建立磁路模型,给出了耦合电感器的设计方法,并对所提出的耦合电感器进行仿真,结合双向DC/DC变换器的实验验证了"I王I"形耦合电感器结构的可行性。