全文获取类型
收费全文 | 130篇 |
免费 | 12篇 |
国内免费 | 9篇 |
专业分类
电工技术 | 5篇 |
综合类 | 5篇 |
化学工业 | 2篇 |
金属工艺 | 2篇 |
机械仪表 | 5篇 |
能源动力 | 1篇 |
轻工业 | 1篇 |
武器工业 | 1篇 |
无线电 | 110篇 |
一般工业技术 | 3篇 |
原子能技术 | 2篇 |
自动化技术 | 14篇 |
出版年
2023年 | 1篇 |
2022年 | 4篇 |
2021年 | 12篇 |
2020年 | 7篇 |
2019年 | 6篇 |
2018年 | 2篇 |
2017年 | 8篇 |
2016年 | 5篇 |
2015年 | 15篇 |
2014年 | 33篇 |
2013年 | 11篇 |
2012年 | 12篇 |
2011年 | 14篇 |
2010年 | 9篇 |
2009年 | 4篇 |
2008年 | 3篇 |
2006年 | 1篇 |
2005年 | 2篇 |
2004年 | 1篇 |
2003年 | 1篇 |
排序方式: 共有151条查询结果,搜索用时 15 毫秒
1.
YingTao Ding YangYang Yan QianWen Chen ShiWei Wang Xiu Chen YueYang Chen 《中国科学:技术科学(英文版)》2014,57(8):1616-1625
Vacuum-assisted spin-coating is an effective polymer filling technology for sidewall insulating of through-silicon-via (TSV). This paper investigated the flow mechanism of the vacuum-assisted polymer filling process based on experiments and numerical simulation, and studied the effect of vacuum pressure, viscosity of polymer and aspect-ratio of trench on the filling performance. A 2D axisymmetric model, consisting of polymer partially filled into the trench and void at the bottom of trench, was developed for the computational fluid dynamics (CFD) simulation. The simulation results indicate that the vacuum-assisted polymer filling process goes through four stages, including bubble formation, bubble burst, air elimination and polymer re-filling. Moreover, the simulation results suggest that the pressure significantly affects the bubble formation and the polymer re-filling procedure, and the polymer viscosity and the trench aspect-ratio influence the duration of air elimination. 相似文献
2.
《Microelectronics Reliability》2014,54(9-10):1953-1958
The effects of silicon etching using the Bosch process and LPCVD oxide deposition on the performance of open TSVs are analyzed through simulation. Using an in-house process simulator, a structure is generated which contains scalloped sidewalls as a result of the Bosch etch process. During the LPCVD deposition step, oxide is expected to be thinner at the trench bottom when compared to the top; however, additional localized thinning is observed around each scallop. The scalloped structure is compared to a structure where the etching step is not performed, but rather a flat trench profile is assumed. Both structures are imported into a finite element tool in order to analyze the effects of processing on device performance. The scalloped structure is shown to have an increased resistance and capacitance when compared to the flat TSV. Additionally, the scalloped TSV does not perform as well at high frequencies, where the signal loss is shown to increase. However, the scallops allow the TSV to respond better to an applied stress. This is due to the scallops’ enhanced range of motion and displacement, meaning they can compensate for the stress along the entire sidewall and not only on the TSV top, as in the flat structure. 相似文献
3.
《Microelectronics Reliability》2014,54(9-10):2133-2137
Through silicon vias are the components in three-dimensional integrated circuits, which are responsible for the vertical connection inside the dies. In this work we present studies about the reliability of open through silicon vias against electromigration. A two-step approach is followed. In the first step the stress development of a void free structure is analysed by means of simulation to find the locations, where voids due to stress are most probably nucleated. In the second step, voids are placed in the through silicon vias and their evolution is traced including the increase of resistance. The resistance raises more than linearly in time and shows an abrupt open circuit failure. These results are in good agreement with results of time accelerated electromigration tests. 相似文献
4.
Jian-Yu Shih Yen-Chi Chen Chih-Hung Chiu Chung-Lun Lo Chi-Chung Chang Kuan-Neng Chen 《Nanoscale research letters》2014,9(1):541
This paper presents one wafer level packaging approach of quartz resonator based on through-silicon via (TSV) interposer with metal or polymer bonding sealing of frequency components. The proposed silicon-based package of quartz resonator adopts several three-dimensional (3D) core technologies, such as Cu TSVs, sealing bonding, and wafer thinning. It is different from conventional quartz resonator using ceramic-based package. With evaluation of mechanical structure design and package performances, this quartz resonator with advanced silicon-based package shows great manufacturability and excellent performance to replace traditional metal lid with ceramic-based interposer fabrication approach. 相似文献
5.
Hirofumi Chiba Yukio Suzuki Yoshiaki Yasuda Mitsuyasu Kumagai Takaaki Koyama Shuji Tanaka 《Electrical Engineering in Japan》2021,214(1):62-68
This paper reports a deep‐ultraviolet LED (deep‐UV‐LED) package based on silicon MEMS process technology (Si‐PKG). The package consists of a cavity formed by silicon crystalline anisotropic etching, through‐silicon vias (TSVs) filled with electroplated Cu, bonding metals made of electroplated Ni/AuSn and a quartz lid for hermetic sealing. A deep‐UV LED die is directly mounted in the Si‐PKG by AuSn eutectic bonding without a submount. It has advantages in terms of size, heat dissipation, light utilization efficiency, productivity and cost over conventional AlN ceramic packages. We confirmed a light output of 30 mW and effective reflection on Si (111) cavity slopes in the Si‐PKG. Based on simulation, further improvement of the optical output is expected by optimizing DUV‐LED die mount condition. 相似文献
6.
硅通孔TSV发生开路故障和泄漏故障会降低三维集成电路的可靠性和良率,因此对绑定前的TSV测试尤为重要。现有CAF-WAS测试方法对泄漏故障的测试优于其他方法(环形振荡器等),缺点是该方法不能测试开路故障。伪泄漏路径思想的提出,解决了现有CAF-WAS方法不能对开路故障进行测试的问题。另外,重新设计了等待时间产生电路,降低了测试时间开销。HSPICE仿真结果显示,该方法能准确预测开路和泄漏故障的范围,测试时间开销仅为现有同类方法的25%。 相似文献
7.
针对三维芯片中硅通孔(through-silicon via, TSV)的准确电学建模问题,本文提出了一种电阻电容(RC)电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走(floating random walk, FRW)算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。 相似文献
8.
9.
Mohamed Abouelatta-Ebrahim Olivier Valorge Francis Calmon 《Microelectronics Journal》2011,42(2):316-324
This paper is essentially composed of two parts for future synthesis. We developed 2D and 3D simulations, starting from a 0.35 μm standard CMOS technology, focusing on through silicon via or redistribution layer induced coupling; nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter are investigated. We also study stacked devices in 3D circuits, in the radiofrequency range, and propagation of electromagnetic waves along some interconnections with discontinuities. This study is performed in the time domain—a finite-difference time-domain method is applied to the analysis of some vias flanked by two striplines, all embedded in silicon. Electric and magnetic field distributions, transmission and reflexion parameters, and pulse propagations along a transverse via are presented. 相似文献
10.
后摩尔时代的封装技术 总被引:4,自引:2,他引:2
童志义 《电子工业专用设备》2010,39(6):1-8
介绍了在高性能的互连和高速互连芯片(如微处理器)封装方面发挥其巨大优势的TSV互连和3D堆叠的三维封装技术。采用系统级封装(SiP)嵌入无源和有源元件的技术,有助于动态实现高度的3D-SiP尺寸缩减。将多层芯片嵌入在内核基板的腔体中;采用硅的后端工艺将无源元件集成到硅衬底上,与有源元件芯片、MEMS芯片一起形成一个混合集成的器件平台。在追求具有更高性能的未来器件的过程中,业界最为关注的是采用硅通孔(TSV)技术的3D封装、堆叠式封装以及类似在3D上具有优势的技术,并且正悄悄在技术和市场上取得实实在在的进步。随着这些创新技术在更高系统集成中的应用,为系统提供更多的附加功能和特性,推动封装技术进入后摩尔时代。 相似文献