A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture

A fully pipelined 10B/8 B decoder is presented with shorter critical path than before, and so its speed is improved greatly. Based on the proposed architecture, a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375 μm<'2>. Measurement results show that the de- coder works well and its speed can be up to 6.25 Gbps. At a 1.8 V power supply, the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.