Power·delay product in COSMOS logic circuits |
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Authors: | Ahmad Al-Ahmadi Savas Kaya |
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Affiliation: | (1) School of Electrical Engineering & Computer Science Russ College of Engineering and Technology, Ohio University, Athens, OH 45701, USA |
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Abstract: | In this simulation work, we use COSMOS logic devices—a novel single gate CMOS architecture recently announced 1]—in multi-input
logic gates, assessing its performance in terms of power·delay product. We consider three different multi-input logic circuits:
a two-input NOR gate, a three-input NOR gate, and a three-input composite NOR/NAND (NORAND) gate. For this power·delay analysis,
the transient TCAD simulations are employed in a mixed-mode approach where circuit and device simulations are coupled together,
culminating in the delay response of the circuits as well as the static/dynamic current components. The analysis shows that
all circuits, except the 3-input NOR gate, has acceptable characteristics at low-power applications and static leakage limits
all COSMOS circuits at high-bias conditions. |
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Keywords: | CMOS COSMOS SiGe MOSFET TCAD SOI Power delay product |
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