| 12Gb/s 0.25μm CMOS低功耗1:4分接器 |
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| 引用本文： | 丁敬峰,王志功,朱恩,章丽,王贵.12Gb/s 0.25μm CMOS低功耗1:4分接器[J].半导体学报,2006,27(1). |
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| 作者姓名： | 丁敬峰 王志功 朱恩 章丽 王贵 |
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| 作者单位： | 东南大学射频与光电集成电路研究所,南京,210096 |
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| 摘 要： | 实现了一种能运用于光传输系统SONET OC-192的低功耗单级分接器,其工作速率高达12Gb/s.该电路采用了特征栅长为0.25μm的TSMC混和信号CMOS工艺.所有的电路都采用了源极耦合逻辑,在抑制共模噪声的同时达到尽可能高的工作速率.该分接器具有利用四分之一速率的正交时钟来实现单级分接的特征,减少了分接器器件,降低了功耗.通过在晶圆测试,该芯片在输入12Gb/s长度为231-1伪随机码流时,分接功能正确.芯片面积为0.9mm×0.9mm,在2.5V单电源供电的情况下的典型功耗是210mW.
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| 关 键 词： | 分接器 锁存器 CMOS 光接收机 |
12Gb/s 0. 25μm CMOS Low-Power 1: 4 Demultiplexer |
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| Ding Jingfeng,Wang Zhigong,Zhu En,Zhang Li,Wang Gui.12Gb/s 0. 25μm CMOS Low-Power 1: 4 Demultiplexer[J].Chinese Journal of Semiconductors,2006,27(1). |
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| Authors: | Ding Jingfeng Wang Zhigong Zhu En Zhang Li Wang Gui |
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| Abstract: | A low power 12Gb/s single-stage 1: 4 demultiplexer (DEMUX) applied in SONET OC-192 is realizedin TSMC's mix-signal 0.25μm CMOS. All of the circuits are in source coupled FET logic (SCFL) to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0.9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply. |
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| Keywords: | demultiplexer latch CMOS optical receiver |
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